-
公开(公告)号:US20230240005A1
公开(公告)日:2023-07-27
申请号:US17928703
申请日:2021-06-10
Applicant: LG INNOTEK CO., LTD.
Inventor: Yong Suk KIM , Jeong Han KIM , Moo Seong KIM
CPC classification number: H05K1/0296 , H05K1/115
Abstract: A circuit board according to an embodiment comprises: an insulation layer; a circuit pattern disposed on the upper surface or under the lower surface of the insulation layer; and a buffer layer disposed on at least one surface of the upper surface and the lower surface of the insulation layer, wherein the buffer layer includes carbon, nitrogen, and oxygen, the ratio of the nitrogen to the carbon ((carbon/nitrogen)*100) is 5 to 15, and the ratio of the oxygen to the carbon ((carbon/oxygen)*100) is 15 to 30.
-
公开(公告)号:US20240043654A1
公开(公告)日:2024-02-08
申请号:US18021632
申请日:2021-08-17
Applicant: LG INNOTEK CO., LTD.
Inventor: Byeong Kyun CHOI , Min Young HWANG , Moo Seong KIM , Jin Seok LEE
IPC: C08K3/22 , C08K3/34 , H05K1/03 , H01L23/498
CPC classification number: C08K3/22 , C08K3/34 , H05K1/036 , H05K1/0373 , H01L23/49894 , H01L23/49822 , C08K2003/2244 , C08K2003/2241 , H05K2201/0242 , H05K2201/0209 , H05K2201/0269
Abstract: A resin composition for a semiconductor package according to an embodiment includes a resin composition that is a composite of a resin and a filler disposed in the resin, wherein the filler includes at least one concave portion provided on a surface, wherein a content of the filler has a range of 10 vol. % to 40 vol % of a total volume of the resin composition, and wherein a porosity corresponds to a volume occupied by the concave portion in a total volume of the filler and has a range of 20% to 35%.
-
公开(公告)号:US20220151068A1
公开(公告)日:2022-05-12
申请号:US17430708
申请日:2020-02-10
Applicant: LG INNOTEK CO., LTD.
Inventor: Min Young HWANG , Moo Seong KIM , Byeong Kyun CHOI
Abstract: A circuit board according to one embodiment comprises a first insulation layer, a circuit pattern on the first insulation layer, and a second insulation layer on the circuit pattern, wherein a heat transfer member is arranged inside the first insulation layer and/or the second insulation layer, and the heat transfer member is arranged while coming in contact with a side surface of the insulation layer.
-
公开(公告)号:US20240120243A1
公开(公告)日:2024-04-11
申请号:US18263603
申请日:2021-04-26
Applicant: LG INNOTEK CO., LTD.
Inventor: Jong Bae SHIN , Moo Seong KIM , Soo Min LEE , Jae Hun JEONG
IPC: H01L23/13 , H01L21/48 , H01L23/498 , H05K1/18 , H05K3/46
CPC classification number: H01L23/13 , H01L21/4857 , H01L23/49822 , H01L23/49838 , H05K1/183 , H05K3/4644 , H05K2203/0195
Abstract: A circuit board according to an embodiment includes a first insulating layer; a second insulating layer disposed on the first insulating layer and including a cavity; and a plurality of pads disposed on the first insulating layer and having top surfaces exposed through the cavity; wherein the cavity of the second insulating layer includes: a bottom surface positioned higher than a top surface of the first insulating layer; and an inner wall extending from the bottom surface, wherein the inner wall is perpendicular to top or bottom surface of the second insulating layer, wherein the bottom surface of the cavity includes: a first bottom surface positioned lower than a top surface of the pad and positioned outside an arrangement region of the plurality of pads; and a second bottom surface positioned lower than the top surface of the pad and positioned inside the arrangement region of the plurality of pads, and wherein a height of the first bottom surface is different from a height of the second bottom surface.
-
公开(公告)号:US20230300977A1
公开(公告)日:2023-09-21
申请号:US18009453
申请日:2021-06-11
Applicant: LG INNOTEK CO., LTD.
Inventor: Se Woong NA , Jung Eun HAN , Moo Seong KIM
CPC classification number: H05K1/0298 , H05K3/28
Abstract: A circuit board according to an embodiment includes: an insulating layer including first to third regions; an outer layer circuit pattern disposed on an upper surface of the first to third regions of the insulating layer; and a solder resist including a first part disposed on the first region of the insulating layer, a second part disposed on the second region, and a third part disposed on the third region, wherein the outer layer circuit pattern includes: a first trace disposed on an upper surface of the first region of the insulating layer; and a second trace disposed on an upper surface of the third region of the insulating layer; wherein a height of the first trace is different from a height of the second trace; and an upper surface of the first part of the solder resist is positioned lower than an upper surface of the first trace.
-
公开(公告)号:US20240324102A1
公开(公告)日:2024-09-26
申请号:US18577077
申请日:2022-07-08
Applicant: LG INNOTEK CO., LTD.
Inventor: Byeong Kyun CHOI , Moo Seong KIM , Woo Seop SIM
IPC: H05K1/11 , H01L23/498 , H05K1/09 , H05K1/18
CPC classification number: H05K1/115 , H01L23/49822 , H05K1/09 , H05K1/181 , H05K2201/09827
Abstract: A circuit board according to an embodiment includes an insulating layer, a first circuit pattern layer disposed on the insulating layer; a second circuit pattern layer disposed below the insulating layer; and a via passing through the insulating layer and connecting the first circuit pattern layer and the second circuit pattern layer, wherein the via has a first width at an upper surface and a second width less than the first width at a first region between the upper surface and a lower surface, wherein the first region is a region with a minimum width among all regions of the via, and wherein the second width satisfies a range of 70% to 99% of the first width.
-
公开(公告)号:US20200236789A1
公开(公告)日:2020-07-23
申请号:US16651143
申请日:2018-09-18
Applicant: LG INNOTEK CO., LTD.
Inventor: Hee Young CHUNG , Jae Man PARK , Moo Seong KIM
Abstract: A printed circuit board according to one embodiment of the present invention comprises an insulation board and a plurality of metal electrodes disposed on the insulation board, wherein: the plurality of metal electrodes include a first electrode and a second electrode; the first electrode includes a first surface parallel to an upper surface of the insulation board, a second surface facing the first surface, a first side surface disposed between the first surface and the second surface, and a second side surface facing the first side surface; a part of the first side surface and a part of the second side surface protrude toward the outside of the first electrode in the direction parallel to the upper surface of the insulation board; the first side surface protrudes farther in an area adjacent to the first surface than in an area adjacent to the second surface; and the second side surface protrudes farther in the area adjacent to the second surface than in the area adjacent to the first surface.
-
公开(公告)号:US20140251976A1
公开(公告)日:2014-09-11
申请号:US14353199
申请日:2012-10-19
Applicant: LG INNOTEK CO., LTD.
Inventor: Ick Chan KIM , Moo Seong KIM
CPC classification number: C23C26/00 , C23C16/4581 , H01L21/67103
Abstract: Disclosed are a hot plate and a method of manufacturing the same. The method includes the steps of preparing a first barrier layer, laminating a first heat transfer layer on the first barrier layer, and laminating a second barrier layer on the first heat transfer layer. The first barrier layer or the second barrier layer includes a plurality of first sub-nano-barrier layers and a plurality of second sub-nano-barrier layers. The hot plate includes a first barrier layer, a first heat transfer layer on the first barrier layer, and a second barrier layer on the first heat transfer layer. The first barrier layer or the second barrier layer includes a plurality of first sub-nano-barrier layers and a plurality of second sub-nano-barrier layers.
Abstract translation: 公开了一种热板及其制造方法。 该方法包括以下步骤:制备第一阻挡层,在第一阻挡层上层叠第一传热层,以及在第一传热层上层压第二阻挡层。 第一阻挡层或第二阻挡层包括多个第一亚纳米阻挡层和多个第二亚纳米阻挡层。 热板包括第一阻挡层,第一阻挡层上的第一传热层和第一传热层上的第二阻挡层。 第一阻挡层或第二阻挡层包括多个第一亚纳米阻挡层和多个第二亚纳米阻挡层。
-
公开(公告)号:US20250040032A1
公开(公告)日:2025-01-30
申请号:US18580365
申请日:2022-08-10
Applicant: LG INNOTEK CO., LTD.
Inventor: Jong Bae SHIN , Moo Seong KIM , Soo Min LEE , Jae Hun JEONG
Abstract: A circuit board according to an embodiment includes a first substrate layer; and a second substrate layer disposed on the first substrate layer and including a cavity, wherein the cavity of the second substrate layer includes a first part disposed adjacent to an upper surface of the second substrate layer and having a first inclination such that a width gradually decreases toward a lower surface of the second substrate layer; and a second part disposed below the first part adjacent to the lower surface of the second substrate layer and having a second inclination such that a width gradually decreases toward the lower surface of the second substrate layer, and the first inclination of the first part relative to a bottom surface of the cavity is greater than the second inclination of the second part relative to the bottom surface of the cavity, and a vertical length of the first part is different from a vertical length of the second part.
-
公开(公告)号:US20230240008A1
公开(公告)日:2023-07-27
申请号:US18010921
申请日:2021-06-17
Applicant: LG INNOTEK CO., LTD.
Inventor: Jeong Han KIM , Yong Suk KIM , Moo Seong KIM
CPC classification number: H05K1/056 , B32B27/20 , B32B3/30 , B32B3/02 , B32B7/02 , B32B15/043 , B32B15/20 , B32B15/14 , B32B2255/06 , B32B2255/205 , B32B2255/26 , B32B2307/538 , B32B2264/1055 , B32B2264/302 , B32B2260/021 , B32B2260/046 , B32B2307/30 , B32B2307/204 , B32B2457/08
Abstract: A resin coated copper according to an embodiment includes: an insulating layer including a resin and a filler dispersed in the resin; and a copper foil layer disposed on the insulating layer, wherein the insulating layer has a plurality of pores formed on a surface in contact with the copper foil layer, and the plurality of pores have a width of 200 nm to 350 nm.
-
-
-
-
-
-
-
-
-