公开(公告)号：US11887686B2

公开(公告)日：2024-01-30

申请号：US17357265

申请日：2021-06-24

申请人： University of Florida Research Foundation, Incorporated ,  Washington University

发明人： Yier Jin ,  Yichen Jiang ,  Xuan Zhang ,  Huifeng Zhu ,  Xiaolong Guo

IPC分类号： G06F21/57 ,  G11C11/406 ,  G11C11/4076 ,  G11C29/52 ,  G11C11/4096 ,  G11C7/24 ,  G11C11/4078 ,  G11C29/04 ,  G11C29/20

CPC分类号： G11C29/52 ,  G11C7/24 ,  G11C11/4076 ,  G11C11/4078 ,  G11C11/4096 ,  G11C11/40611 ,  G11C29/04 ,  G11C29/20

摘要： Embodiments provide for predicting rowhammer attack vulnerability of one or more memory cells of a direct random access memory (DRAM) chip, the DRAM chip including a plurality of memory cells. An example method, determines, for each memory cell of a subset of memory cells of the plurality of memory cells, a leakage time t, a resistance of intrinsic leakage RL based at least in part on the leakage time t, an activation time of an adjacent aggressor row to flip a bit in the memory cell, a resistance of coupling leaking RSW based at least in part on the activation time, and a toggling count. The method identifies, based at least in part on one or more of the RSW, RL, or toggling count, whether the direct random memory access (DRAM) chip is vulnerable to a rowhammer attack.

公开(公告)号：US20240029788A1

公开(公告)日：2024-01-25

申请号：US18339168

申请日：2023-06-21

申请人： Micron Technology, Inc.

发明人： Violante Moschiano ,  Andrea D'Alessandro ,  Andrea Giovanni Xotta

IPC分类号： G11C11/56 ,  G06F11/10 ,  G11C16/34 ,  G11C16/26 ,  G11C29/52 ,  H03M13/45

CPC分类号： G11C11/5642 ,  G06F11/1068 ,  G06F11/1012 ,  G11C16/34 ,  G11C16/26 ,  G11C29/52 ,  H03M13/45 ,  G11C2029/0411

摘要： The present disclosure includes apparatuses and methods for determining soft data. A number of embodiments include determining soft data associated with a data state of a memory cell. In a number of embodiments, the soft data may be determined by performing a single stepped sense operation on the memory cell.

公开(公告)号：US20240021266A1

公开(公告)日：2024-01-18

申请号：US17866558

申请日：2022-07-18

申请人： Winbond Electronics Corp.

发明人： Yao-Ting Tsai ,  Che-Fu Chuang

IPC分类号： G11C29/00 ,  G11C29/52

CPC分类号： G11C29/72 ,  G11C29/785 ,  G11C29/52

摘要： A memory array is provided. The memory array includes multiple memory blocks, each including multiple data storage regions and multiple groups of word lines. Each group of word lines extend across one of the memory blocks. The groups of word lines are connected to multiple overlying signal lines through multiple groups of first word line contact regions in the memory blocks and multiple second word line contact regions between the memory blocks.

公开(公告)号：US20240013849A1

公开(公告)日：2024-01-11

申请号：US17858357

申请日：2022-07-06

申请人： Innogrit Technologies Co., Ltd.

发明人： Chenrong XIONG ,  Jie CHEN

IPC分类号： G11C29/52 ,  G11C29/50 ,  G11C7/10

CPC分类号： G11C29/52 ,  G11C29/50004 ,  G11C7/1039

摘要： Systems and methods are provided for determining optimal read reference voltages used for reading data in non-volatile storage devices. A method may include reading data stored in a non-volatile storage device using a group of soft read reference voltages, decoding the data and obtaining the number of ones and number of zeros for each of a plurality of zones delineated by the soft read reference voltages, determining that one of the soft read reference voltages is a boundary of a zone in which a comparison result of the number of ones compared to the number of zeros is greater than zero and a boundary of another zone in which a comparison result is less than zero and setting the soft read reference voltage adjusted by an adjustment as an optimal read reference voltage. The adjustment may be obtained based on the two comparison results.

公开(公告)号：US11868488B2

公开(公告)日：2024-01-09

申请号：US17994680

申请日：2022-11-28

申请人： Micron Technology, Inc.

发明人： Antonino Mondello ,  Carmelo Condemi ,  Francesco Tomaiuolo ,  Tommaso Zerilli

IPC分类号： G06F11/30 ,  G06F12/14 ,  G06F21/60 ,  H04L9/32 ,  H03M13/29 ,  G06F11/10 ,  G11C29/52 ,  G06F21/64 ,  G06F21/79

CPC分类号： G06F21/602 ,  G06F11/1068 ,  G06F21/64 ,  G06F21/79 ,  G11C29/52 ,  H03M13/2906 ,  H04L9/3242 ,  H04L9/3278

摘要： An apparatus, such as a memory system (e.g., a NAND memory system), can have a controller with a first error correction code component and a memory device (e.g., a NAND memory device) coupled to the controller. The memory device can have an array of memory cells, a second error correction code component coupled to the array and configured to correct data from the array, and a cryptographic component coupled to receive the corrected data from the second error correction code component.

公开(公告)号：US20240005969A1

公开(公告)日：2024-01-04

申请号：US18068914

申请日：2022-12-20

申请人： Kioxia Corporation

发明人： Shohei ASAMI ,  Yoshihisa KOJIMA

IPC分类号： G11C7/10 ,  G11C29/52

CPC分类号： G11C7/1096 ,  G11C7/1069 ,  G11C29/52

摘要： According to one embodiment, a memory system includes a semiconductor memory, a controller, and a first circuit. The semiconductor memory includes a nonvolatile memory cell. The controller is configured to cause the semiconductor memory to execute first and second write operations. The first write operation writes a first bit into the memory cell. The second write operation writes first data based on the first bit and a second bit into the memory cell. The first circuit checks whether or not the first bit includes a bit error. The controller is configured to cause the semiconductor memory to execute, in the second write operation, writing of the first data including the second bit and a third bit obtained by correcting the bit error of the first bit, in a case that the first bit includes the bit error.

公开(公告)号：US11854612B1

公开(公告)日：2023-12-26

申请号：US18373071

申请日：2023-09-26

申请人： Vervain, LLC

发明人： G. R. Mohan Rao

IPC分类号： G11C11/56 ,  G06F12/02 ,  G11C16/34 ,  G06F11/10 ,  G11C29/52 ,  G11C29/00 ,  G11C16/16

CPC分类号： G11C11/5635 ,  G06F11/1068 ,  G06F11/1072 ,  G06F12/0246 ,  G11C11/5621 ,  G11C11/5678 ,  G11C16/16 ,  G11C16/3495 ,  G11C29/52 ,  G11C29/76 ,  G06F2212/7202 ,  G11C2211/5641

摘要： A method for storing data comprises maintaining an address table for a memory space containing volatile memory and nonvolatile memory space. The nonvolatile memory space includes both multi-level cell (MLC) space and single level cell (SLC) space and the volatile memory includes a random access volatile memory element. An address table maps logical and physical addresses adaptable to the system by the address table. The mapping is performed as necessitated by the system to maximize lifetime maps data in at least one of volatile or nonvolatile memories. Storing received data within a controller memory associated with the at least one controller. Controlling access of the MLC and SLC nonvolatile memory elements and the random access volatile memory element for storage of the received data. Transferring the stored received data from the controller memory to a given one of the MLC nonvolatile memory elements in an associated MLC memory module, operable to store the received data in the given one given one of the MLC nonvolatile memory element as stored data. Retaining the received data in the random access volatile memory as retained data associated with the stored data. Performing a data integrity test on the stored data in the given one of the MLC nonvolatile memory elements in the associated one of the MLC memory modules after at least a Write access operation performed thereon. The performing of the data integrity test further comprising reading the stored data to the controller memory and comparing the stored data in the controller memory in the given one of the MLC nonvolatile memory elements to the retained data that was associated with the stored data in the random access volatile memory by the controller during the Write access operation. Remapping, responsive to a failure of the data integrity test performed on the stored data by the controller, the address space to a different physical range of addresses. Transferring data corresponding to the retained data to those remapped physical address from those physical addresses determined to have failed the data integrity test.

公开(公告)号：US11847023B2

公开(公告)日：2023-12-19

申请号：US17963999

申请日：2022-10-11

申请人： Silicon Motion, Inc.

发明人： Tsung-Chieh Yang ,  Hong-Jung Hsu ,  Jian-Dong Du

IPC分类号： G06F11/00 ,  G06F11/10 ,  G11C29/52 ,  G11C11/56 ,  G11C16/26 ,  G11C16/10 ,  G11C16/04

CPC分类号： G06F11/1068 ,  G06F11/1072 ,  G06F11/1076 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/26 ,  G11C29/52 ,  G11C16/0483 ,  G11C2211/5641

摘要： A flash memory method includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate first corresponding parity check code to store the groups of data and first corresponding parity check code into flash memory module as first blocks; reading out the groups of data from first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon randomized data to generate second corresponding parity check code; and, storing randomized data and second corresponding parity check code into flash memory module as second block; a cell of first block is used for storing data of first bit number which is different from second bit number corresponding to a cell of second block.

公开(公告)号：US20230402112A1

公开(公告)日：2023-12-14

申请号：US17838481

申请日：2022-06-13

申请人： Western Digital Technologies, Inc.

发明人： Eran Sharon ,  Ariel Navon ,  Alexander Bazarsky ,  David Avraham ,  Nika Yanuka ,  Idan Alrod ,  Tsiko Shohat Rozenfeld ,  Ran Zamir

IPC分类号： G11C16/34 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/08 ,  G11C29/52

CPC分类号： G11C16/3459 ,  G11C16/3495 ,  G11C16/102 ,  G11C16/14 ,  G11C16/26 ,  G11C16/08 ,  G11C29/52

摘要： A storage system has an inference engine that can infer a read threshold based on a plurality of parameters of the memory. The read threshold can be used in reading a wordline in the memory during a regular read operation or as part of an error handling process. Using this machine-learning-based approach to infer a read threshold can provide significant improvement in read threshold accuracy, which can reduce bit error rate and improve latency, throughput, power consumption, and quality of service.

公开(公告)号：US20230395184A1

公开(公告)日：2023-12-07

申请号：US17959191

申请日：2022-10-03

申请人： Micron Technology, Inc.

发明人： Danilo Caraccio ,  Antonino Caprì ,  Daniele Balluchi ,  Massimiliano Patriarca

IPC分类号： G11C29/52 ,  G11C11/4093 ,  G11C11/406

CPC分类号： G11C29/52 ,  G11C11/4093 ,  G11C11/40615

摘要： A soft post package repair (sPPR) request is detected. Data stored in a target row of a memory array associated with the sPPR request is written to a buffer. Execution of non-maintenance requests on the target row is suspended. Responsive to suspension of execution of non-maintenance requests on the target row, the sPPR request is executed on the target row. Subsequent to completion of the sPPR request, execution of non-maintenance requests on the target row is resumed and the data stored in the buffer is written to the repaired target row.