公开(公告)号：US12086458B2

公开(公告)日：2024-09-10

申请号：US17729980

申请日：2022-04-26

Applicant: Micron Technology, Inc.

Inventor： Tomoko Ogura Iwasaki ,  Manik Advani

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0679

Abstract: A memory system includes a memory device comprising a programming buffer and a content addressable memory (CAM) block. The memory system further includes a processing device that receives a plurality of data entries to be stored at the memory device and stores the plurality of data entries in a plurality of pages of the programming buffer, each of the plurality of pages of the programming buffer comprising a respective subset of the plurality of data entries. The processing device further initiates a conversion operation to copy the plurality of data entries from the programming buffer to the CAM block. The conversion operation includes reading respective portions of each data entry in each respective subset of the plurality of data entries from the plurality of pages of the programming buffer, and writing the respective portions to respective CAM pages of the CAM block.

公开(公告)号：US12086296B2

公开(公告)日：2024-09-10

申请号：US17234105

申请日：2021-04-19

Applicant: Micron Technology, Inc.

Inventor： Lance W. Dover

IPC: G06F21/78 ,  G06F21/44 ,  G06F21/62 ,  G06F21/64 ,  H04L9/06 ,  H04L9/08 ,  H04L9/32

CPC classification number: G06F21/78 ,  G06F21/44 ,  G06F21/6218 ,  G06F21/64 ,  H04L9/0643 ,  H04L9/0877 ,  H04L9/0897 ,  H04L9/3234 ,  H04L9/3242 ,  H04L9/3263

Abstract: A device to secure data storage may include circuitry that switches a communication circuit to a memory from a derived secret generator based on an access command.

公开(公告)号：US12086058B2

公开(公告)日：2024-09-10

申请号：US18206958

申请日：2023-06-07

Applicant: Micron Technology, Inc.

Inventor： Zhengang Chen ,  Jianmin Huang

IPC: G06F12/02 ,  G06F12/14 ,  G06F13/16 ,  G11C11/56 ,  H04L9/06 ,  H04L9/08

CPC classification number: G06F12/0246 ,  G06F12/1408 ,  G06F13/1668 ,  G11C11/5628 ,  H04L9/0662 ,  H04L9/0869 ,  G06F2212/7207

Abstract: Disclosed in some examples are methods, systems, devices, and machine-readable mediums that provide for techniques for scrambling and/or updating meta-data that enable an efficient internal copyback operation. In some examples, improved data distribution techniques decouple the scrambling key from a physical address to allow for copyback operations while maintaining data distribution requirements across a memory device. The controller may generate a seed value that is used by a scrambling algorithm to scramble the host-data and meta-data prior to the data being written. The seed value is then encoded and written to the page with encoded versions of the scrambled user data and meta-data—the random seed is written without scrambling the random seed.

公开(公告)号：US12086028B2

公开(公告)日：2024-09-10

申请号：US18064203

申请日：2022-12-09

Applicant: Micron Technology, Inc.

Inventor： Sivagnanam Parthasarathy ,  Kishore Kumar Muchherla ,  Akira Goda ,  Mustafa N. Kaynak

IPC: G06F11/10 ,  H03M13/11

CPC classification number: G06F11/1068 ,  H03M13/1102

Abstract: A memory device to use added known data as part of data written to memory cells with redundant data generated according to an error correction code (ECC). The code rate of the ECC may limit its capability to recover from excessive errors in the stored data. To reduce the errors, the added data retrieved from the memory cells can be corrected without using the ECC. Subsequently, remaining errors can be corrected via the ECC. Optionally, the added data can be configured to be the same as the data represented by an erased state of a subset of the memory cells such that when the subset is used to store the added data, the subset remains in the erased state to reduce wearing. Different subsets can be used to store added data for different write operations to distribute the benefit of reduced wearing.

公开(公告)号：US12086005B2

公开(公告)日：2024-09-10

申请号：US17729813

申请日：2022-04-26

Applicant: Micron Technology, Inc.

Inventor： Martin Brox ,  Thomas Hein ,  Wolfgang Anton Spirkl ,  Andrea Sorrentino ,  Peter Mayer

IPC: G06F1/28 ,  G06F1/20

CPC classification number: G06F1/28 ,  G06F1/206

Abstract: Methods, systems, and devices for tracking a reference voltage (also referred to as VREFD) after boot-up are described. For example, a host device or a memory device may determine a temperature value associated with the memory device. The host device or the memory device may select a reference voltage offset value for the memory device based on mapping the temperature value associated with the memory device to a relationship between reference voltage offset values and temperature differential values associated with the memory device. The host device or the memory device may adjust a reference voltage value associated with the memory device based on the reference voltage offset value. The host device, or the memory device, may operate the memory device in accordance with the reference voltage value based on adjusting the reference voltage value.

公开(公告)号：US20240296896A1

公开(公告)日：2024-09-05

申请号：US18657672

申请日：2024-05-07

Applicant: Micron Technology, Inc.

Inventor： Patrick Robert Khayat ,  James Fitzpatrick ,  AbdelHakim S. Alhussien ,  Sivagnanam Parthasarathy

IPC: G11C16/34 ,  G06F18/214 ,  G06N20/00 ,  G11C7/02 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30

CPC classification number: G11C16/3431 ,  G06F18/214 ,  G06N20/00 ,  G11C7/02 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30

Abstract: A memory device to perform a read disturb mitigation operation. For example, the memory device can measure signal and noise characteristics of a group of memory cells to determine an optimized read voltage of the group of memory cells and determine a margin of read disturb accumulated in the group of memory cells. Subsequently, the memory device can identify the group of memory cells for the read disturb mitigation operation based on the margin of read disturb and a predetermined threshold.

公开(公告)号：US20240296892A1

公开(公告)日：2024-09-05

申请号：US18659845

申请日：2024-05-09

Applicant: Micron Technology, Inc.

Inventor： Zhongyuan Lu ,  Niccolo' Righetti

IPC: G11C16/16 ,  G11C7/04 ,  G11C16/08 ,  G11C16/26 ,  G11C16/32

CPC classification number: G11C16/16 ,  G11C7/04 ,  G11C16/08 ,  G11C16/26 ,  G11C16/32

Abstract: Bake temperatures for memory blocks can be determined as part of an operation to allocate memory blocks for us by a memory device. If a temperature of a particular memory block among the plurality of memory blocks meets or exceeds a threshold operational temperature corresponding to a memory device containing the plurality of memory blocks, the particular memory block can be allocated for receipt and/or storage of data.

公开(公告)号：US20240296879A1

公开(公告)日：2024-09-05

申请号：US18404587

申请日：2024-01-04

Applicant: Micron Technology, Inc.

Inventor： Christopher Joseph Bueb ,  Zheng Wang

IPC: G11C11/406 ,  G11C11/4096 ,  G11C29/52

CPC classification number: G11C11/40618 ,  G11C11/40626 ,  G11C11/4096 ,  G11C29/52

Abstract: Methods, systems, and devices for data integrity improvement programming techniques are described. A memory system may be pre-programed with data prior to assembling the memory system, where assembling the memory system may adversely affect data integrity of a portion of the data. The data integrity of the portion of the data may be improved by programming additional data to the memory system or adjusting data characteristics associated with the portion of the data. The memory system may perform a start-up procedure in which the memory system may identify an indication to perform a refresh operation. The memory system may perform a refresh operation using the additional data programmed to the memory system or using the adjusted data characteristics to improve the data integrity of the portion of the data and mitigate performance issues otherwise associated with performing the refresh operation.

公开(公告)号：US20240296096A1

公开(公告)日：2024-09-05

申请号：US18588373

申请日：2024-02-27

Applicant: Micron Technology, Inc.

Inventor： Sujeet Ayyapureddi

IPC: G06F11/10

CPC classification number: G06F11/1096

Abstract: Apparatuses, systems, and methods for selectable expansion of error correction capability. A memory includes an error correction code (ECC) circuit which generates a default number of parity bits based on written data, and uses those parity bits to correct error(s) in the data. A setting of the memory may specify some number of extra bits of parity. When enabled the ECC circuit may generate parity include the default parity and the extra parity. The default parity is stored in an ECC column plane. The extra parity is stored in the data column planes. When the extra parity is enabled, the ECC circuit may detect/correct more bits of error in the data.

公开(公告)号：US20240296090A1

公开(公告)日：2024-09-05

申请号：US18415627

申请日：2024-01-17

Applicant: Micron Technology, Inc.

Inventor： Joseph M. MCCRATE ,  Kirthi SHENOY ,  Marco SFORZIN ,  Brian M. TWAIT

IPC: G06F11/10

CPC classification number: G06F11/1044

Abstract: Provided is a memory system comprising a plurality of memory components. The ECC decoding is configured to construct first and second codewords from a single set of data within the plurality of memory components and perform error correction code (ECC) decoding on the first and second codewords received read from the plurality of memory components wherein the ECC decoding is configured to (i) detect random errors in the first received codeword and (ii) use data associated with the detected random errors to correct erasures in the second received codeword.