公开(公告)号：US20170115502A1

公开(公告)日：2017-04-27

申请号：US14920249

申请日：2015-10-22

Applicant: STMicroelectronics, Inc.

Inventor： Chih-Hung TAI ,  Felix KIM ,  Mark A. LYSINGER

IPC: G02B27/64

CPC classification number: G02B27/646

Abstract: Various embodiments provide an optical image stabilization circuit that synchronizes its gyroscope and drive circuit using gyroscope data ready signals and gyroscope reset signals. In response to a gyroscope data ready signal, the optical image stabilization circuit synchronously obtains position measurements of a camera lens when power drive signals are not transitioning from one power level to another power level, and synchronously transitions the power drive signals simultaneously with gyroscope reset signals. By synchronizing the gyroscope and the drive circuit, the gyroscope and other onboard sensing circuits are isolated from noise generated by the drive circuit.

公开(公告)号：US09633986B2

公开(公告)日：2017-04-25

申请号：US15175738

申请日：2016-06-07

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： John H. Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu ,  Edem Wornyo

IPC: H01L49/02 ,  H01L27/01 ,  H01L23/525 ,  H01L21/3105 ,  H01L23/522 ,  H01L21/321

CPC classification number: H01L27/016 ,  H01L21/31053 ,  H01L21/3212 ,  H01L23/5223 ,  H01L23/5228 ,  H01L23/5252 ,  H01L23/5256 ,  H01L28/20 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A sequence of semiconductor processing steps permits formation of both vertical and horizontal nanometer-scale serpentine resistors and parallel plate capacitors within a common structure. The method takes advantage of a CMP process non-uniformity in which the CMP polish rate of an insulating material varies according to a certain underlying topography. By establishing such topography underneath a layer of the insulating material, different film thicknesses of the insulator can be created in different areas by leveraging differential polish rates, thereby avoiding the use of a lithography mask. In one embodiment, a plurality of resistors and capacitors can be formed as a compact integrated structure within a common dielectric block, using a process that requires only two mask layers. The resistors and capacitors thus formed as a set of integrated circuit elements are suitable for use as microelectronic fuses and antifuses, respectively, to protect underlying microelectronic circuits.

公开(公告)号：US09633911B2

公开(公告)日：2017-04-25

申请号：US14668482

申请日：2015-03-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMicroelectronics, Inc. ,  GLOBALFOUNDRIES Inc.

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Qing Liu ,  Nicolas Loubet ,  Scott Luning

IPC: H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01L27/22 ,  H01L43/10 ,  H01L21/84 ,  H01L27/12 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/10 ,  H01L29/16 ,  H01L29/161

CPC classification number: H01L21/845 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/84 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/4966

Abstract: A method for semiconductor fabrication includes providing channel regions on a substrate including at least one Silicon Germanium (SiGe) channel region, the substrate including a plurality of regions including a first region and a second region. Gate structures are formed for a first n-type field effect transistor (NFET) and a first p-type field effect transistor (PFET) in the first region and a second NFET and a second PFET in the second region, the gate structure for the first PFET being formed on the SiGe channel region. The gate structure for the first NFET includes a gate material having a first work function and the gate structures for the first PFET, second NFET and second PFET include a gate material having a second work function such that multi-threshold voltage devices are provided.

公开(公告)号：US09627245B2

公开(公告)日：2017-04-18

申请号：US14197790

申请日：2014-03-05

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Bruce Doris ,  Kangguo Cheng ,  Nicolas Loubet

IPC: H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L29/51 ,  H01L29/04 ,  H01L29/165

CPC classification number: H01L21/76224 ,  H01L29/045 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7853

Abstract: One illustrative method disclosed herein involves, among other things, forming trenches to form an initial fin structure having an initial exposed height and sidewalls, forming a protection layer on at least the sidewalls of the initial fin structure, extending the depth of the trenches to thereby define an increased-height fin structure, with a layer of insulating material over-filling the final trenches and with the protection layer in position, performing a fin oxidation thermal anneal process to convert at least a portion of the increased-height fin structure into an isolation material, removing the protection layer, and performing an epitaxial deposition process to form a layer of semiconductor material on at least portions of the initial fin structure.

公开(公告)号：US09620626B2

公开(公告)日：2017-04-11

申请号：US14272660

申请日：2014-05-08

Applicant: Soitec ,  STMicroelectronics, Inc.

Inventor： Frédéric Allibert ,  Pierre Morin

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/205 ,  H01L21/8238 ,  H01L21/84

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/02614 ,  H01L21/02694 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/205

Abstract: Methods of fabricating semiconductor structures involve the formation of fins for finFET transistors having different stress/strain states. Fins of one stress/strain state may be employed to form n-type finFETS, while fins of another stress/strain state may be employed to form p-type finFETs. The fins having different stress/strain states may be fabricated from a common layer of semiconductor material. Semiconductor structures and devices are fabricated using such methods.

公开(公告)号：US20170092778A1

公开(公告)日：2017-03-30

申请号：US15280879

申请日：2016-09-29

Applicant: STMICROELECTRONICS, INC.

Inventor： John H. ZHANG

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/78642 ,  H01J21/105 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/78696

Abstract: A vacuum channel transistor having a vertical gate-all-around (GAA) architecture provides high performance for high-frequency applications, and features a small footprint compared with existing planar devices. The GAA vacuum channel transistor features stacked, tapered source and drain regions that are formed by notching a doped silicon pillar using a lateral oxidation process. A temporary support structure is provided for the pillar during formation of the vacuum channel. Performance of the GAA vacuum channel transistor can be tuned by replacing air in the channel with other gases such as helium, neon, or argon. A threshold voltage of the GAA vacuum channel transistor can be adjusted by altering dopant concentrations of the silicon pillar from which the source and drain regions are formed.

公开(公告)号：US20170090604A1

公开(公告)日：2017-03-30

申请号：US15276341

申请日：2016-09-26

Applicant: STMICROELECTRONICS, INC.

Inventor： Dominique Paul BARBIER

IPC: G06F3/0354 ,  G06F3/038 ,  G06F3/041 ,  G01L19/14

CPC classification number: G06F3/03545 ,  G01L5/226 ,  G06F3/0383 ,  G06F3/0416 ,  G06F3/0488 ,  G06F2203/04105

Abstract: An encapsulated pressure sensor includes a pressure sensor having a pressure sensing surface and a mounting surface. The mounting surface is attached to a mounting substrate. A fluid contacts the pressure sensing surface of the pressure sensor. A deformable encapsulating member is attached to the mounting substrate and encapsulates the pressure sensor and the fluid.

公开(公告)号：US09604845B2

公开(公告)日：2017-03-28

申请号：US14873091

申请日：2015-10-01

Applicant: STMicroelectronics, Inc.

Inventor： Ming Fang

IPC: H01L21/00 ,  B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00666 ,  B81B7/0029 ,  B81B2203/0181 ,  B81C1/0019 ,  B81C2201/0169 ,  B81C2201/112

Abstract: A method of manufacturing microstructures, such as MEMS or NEMS devices, including forming a protective layer on a surface of a moveable component of the microstructure. For example, a silicide layer may be formed on a portion of at least four different surfaces of a poly-silicon mass that is moveable with respect to a substrate of the microstructure. The process may be self-aligning.

公开(公告)号：US20170084733A1

公开(公告)日：2017-03-23

申请号：US15365640

申请日：2016-11-30

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas LOUBET ,  Pierre MORIN

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/49 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L29/785 ,  H01L27/0886 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/41791 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7849 ,  H01L2029/7858

Abstract: A self-aligned SiGe FinFET device features a relaxed channel region having a high germanium concentration. Instead of first introducing germanium into the channel and then attempting to relax the resulting strained film, a relaxed channel is formed initially to accept the germanium. In this way, a presence of germanium can be established without straining or damaging the lattice. Gate structures are patterned relative to intrinsic silicon fins, to ensure that the gates are properly aligned, prior to introducing germanium into the fin lattice structure. After aligning the gate structures, the silicon fins are segmented to elastically relax the silicon lattice. Then, germanium is introduced into the relaxed silicon lattice, to produce a SiGe channel that is substantially stress-free and also defect-free. Using the method described, concentration of germanium achieved in a structurally stable film can be increased to a level greater than 85%.

公开(公告)号：US09601630B2

公开(公告)日：2017-03-21

申请号：US13931096

申请日：2013-06-28

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: H01L29/775 ,  H01L29/786 ,  H01L29/66 ,  H01L29/40 ,  H01L29/417 ,  H01L29/778 ,  H01L29/41 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/12 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/165

CPC classification number: H01L29/78618 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/127 ,  H01L29/165 ,  H01L29/401 ,  H01L29/413 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42392 ,  H01L29/456 ,  H01L29/4975 ,  H01L29/66431 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7781 ,  H01L29/78696

Abstract: Metal quantum dots are incorporated into doped source and drain regions of a MOSFET array to assist in controlling transistor performance by altering the energy gap of the semiconductor crystal. In a first example, the quantum dots are incorporated into ion-doped source and drain regions. In a second example, the quantum dots are incorporated into epitaxially doped source and drain regions.