公开(公告)号：US20150243361A1

公开(公告)日：2015-08-27

申请号：US14632785

申请日：2015-02-26

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francois Tailliet

IPC: G11C16/14

CPC classification number: G11C16/14 ,  G11C16/0433 ,  G11C16/12 ,  G11C16/349 ,  G11C16/3495

Abstract: A method of programming an EEPROM, including: a first mode where a writing into cells is performed under a first voltage; and a second mode where the writing is performed under a second voltage smaller than the first one.

Abstract translation: 一种编程EEPROM的方法，包括：第一模式，其中在第一电压下执行对单元的写入; 以及在小于第一电压的第二电压下执行写入的第二模式。

公开(公告)号：US09099186B2

公开(公告)日：2015-08-04

申请号：US14293870

申请日：2014-06-02

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francois Tailliet

IPC: G11C16/04 ,  G11C16/02 ,  G11C16/14 ,  G11C16/10 ,  G11C16/06 ,  G11C16/24 ,  G11C16/08 ,  G11C16/16 ,  G11C11/56

CPC classification number: G11C16/14 ,  G11C11/5628 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16

Abstract: The present disclosure relates to a method for writing in an EEPROM memory, the method comprising steps of: storing the bits of a word to be written in first memory units, erasing a word to be modified, formed by first memory cells connected to a word line and first bit lines, reading bits stored in the memory cells of a word line WL , in a first read mode and storing the bits read in second memory units, reading in a second read mode the bits stored in the memory cells of the word line, and programming each memory cell of the word line connected to a memory unit storing a bit in the programmed state of the word to be written, of an erased word or of a word comprising a bit having different states in the first and second read modes.

Abstract translation: 本发明涉及一种在EEPROM存储器中写入的方法，该方法包括以下步骤：将要写入的字的位存储在第一存储单元中，擦除要连接到字的第一存储器单元形成的要修改的字 行和第一位线，以第一读取模式读取存储在字线WL的存储单元中的位，并存储读入第二存储器单元的位，读取第二读取模式存储在存储器单元中的位 并且将连接到存储单元的字线的每个存储器单元编程为存储要写入的字的编程状态的位的擦除字或包括在第一个中包含不同状态的位的字的字 和第二读取模式。

公开(公告)号：US09083487B2

公开(公告)日：2015-07-14

申请号：US13894819

申请日：2013-05-15

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Thierry Meziache

IPC: H04L1/00 ,  H04L9/00 ,  H04W12/06 ,  H04W4/00 ,  H04W12/08

CPC classification number: H04L9/00 ,  H04L1/0041 ,  H04L1/0045 ,  H04W4/80 ,  H04W12/06 ,  H04W12/08

Abstract: The information bits and the parity bits are encrypted in a microcontroller and transmitted on a bus to a transceiver head which forms the frames to be transmitted on a channel from encrypted information bits and from encrypted parity bits received on the bus.

Abstract translation: 信息位和奇偶校验位在微控制器中加密，并在总线上传送到收发器头，收发器头形成要从加密信息位和从总线上接收的加密奇偶校验位在信道上发送的帧。

公开(公告)号：US09081671B2

公开(公告)日：2015-07-14

申请号：US14300877

申请日：2014-06-10

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Hubert Rousseau

IPC: G06F12/00 ,  G06F12/02 ,  G06F3/06 ,  G06F11/14 ,  G11C16/10

CPC classification number: G06F3/0619 ,  G06F3/0604 ,  G06F3/0616 ,  G06F3/064 ,  G06F3/0644 ,  G06F3/065 ,  G06F3/0652 ,  G06F3/0679 ,  G06F11/1435 ,  G06F11/1471 ,  G06F12/0246 ,  G06F12/0253 ,  G06F2212/7202 ,  G06F2212/7205 ,  G06F2212/7207 ,  G06F2212/7211 ,  G11C16/10 ,  G11C16/105

Abstract: A method for writing and reading data memory cells, comprising: defining in a first memory zone erasable data pages and programmable data blocks; and, in response to write commands of data, writing data in erased blocks of the first memory zone, and writing, in a second memory zone, metadata structures associated with data pages and comprising, for each data page, a wear counter containing a value representative of the number of times that the page has been erased.

Abstract translation: 一种用于写入和读取数据存储单元的方法，包括：在第一存储区中定义可擦除数据页和可编程数据块; 并且响应于数据的写入命令，将数据写入第一存储器区域的擦除块中，以及在第二存储器区域中写入与数据页相关联的元数据结构，并且对于每个数据页包括含有值的磨损计数器 代表页面被删除的次数。

公开(公告)号：US20150172851A1

公开(公告)日：2015-06-18

申请号：US14629077

申请日：2015-02-23

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Thierry Meziache

IPC: H04W4/00 ,  H04B1/69

CPC classification number: H04W4/008 ,  G06K7/10306 ,  G06K19/0715 ,  H04B1/69 ,  H04B5/0068 ,  H04W4/80

Abstract: A terminal of a near-field communication system, including at least one element for spreading the spectrum of a received signal.

Abstract translation: 近场通信系统的终端，包括用于扩展接收信号频谱的至少一个元件。

公开(公告)号：US20150117117A1

公开(公告)日：2015-04-30

申请号：US14528785

申请日：2014-10-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Julien Delalleau ,  Arnaud Regnier

IPC: H01L27/115 ,  H01L21/3205 ,  H01L29/788 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  G11C16/14 ,  H01L21/3213

CPC classification number: H01L29/42328 ,  G11C16/0425 ,  G11C16/14 ,  H01L21/28273 ,  H01L21/30604 ,  H01L21/32051 ,  H01L21/32133 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42336 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/7827 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/7883 ,  H01L29/7885

Abstract: The present disclosure relates to a memory cell comprising a vertical selection gate extending in a trench made in a substrate, a floating gate extending above the substrate, and a horizontal control gate extending above the floating gate, wherein the floating gate also extends above a portion of the vertical selection gate over a non-zero overlap distance. Application mainly to the production of a split gate memory cell programmable by hot-electron injection.

Abstract translation: 本公开涉及一种存储单元，其包括在衬底中形成的沟槽中延伸的垂直选择栅极，在衬底上方延伸的浮动栅极以及在浮置栅极上方延伸的水平控制栅极，其中浮动栅极还在部分 的垂直选择门在非零重叠距离上。 主要用于生产通过热电子注入可编程的分离栅极存储单元。

公开(公告)号：US20150117109A1

公开(公告)日：2015-04-30

申请号：US14528780

申请日：2014-10-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco LA ROSA ,  Stephan NIEL ,  Arnaud REGNIER ,  Julien DELALLEAU

IPC: G11C16/10 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/24 ,  G11C16/34 ,  G11C16/3418 ,  H01L27/11524 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/7881

Abstract: The present disclosure relates to a memory comprising at least one word line comprising a row of split gate memory cells each comprising a selection transistor section comprising a selection gate and a floating-gate transistor section comprising a floating gate and a control gate. According to the present disclosure, the memory comprises a source plane common to the memory cells of the word line, to collect programming currents passing through memory cells during their programming, and the selection transistor sections of the memory cells are connected to the source plane. A programming current control circuit is configured to control the programming current passing through the memory cells by acting on a selection voltage applied to a selection line.

Abstract translation: 本公开涉及包括至少一个字线的存储器，该字线包括一行分离栅极存储单元，每行分离栅极存储单元包括选择晶体管部分，该选择晶体管部分包括选择栅极和包括浮置栅极和控制栅极的浮动栅极晶体管部分。 根据本公开，存储器包括与字线的存储器单元共同的源平面，以在编程期间收集通过存储器单元的编程电流，并且存储器单元的选择晶体管部分连接到源极平面。 编程电流控制电路被配置为通过作用于施加到选择线的选择电压来控制通过存储器单元的编程电流。

公开(公告)号：US09019236B2

公开(公告)日：2015-04-28

申请号：US14205157

申请日：2014-03-11

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Laurent Beyly ,  Cyril Troise ,  Maxime Teissier

IPC: G06F3/041 ,  G06F3/044 ,  H03K17/955 ,  H03K17/96

CPC classification number: G06F3/044 ,  G06F3/0416 ,  G06F2203/04101 ,  H03K17/955 ,  H03K17/9622 ,  H03K2217/960725

Abstract: The present disclosure relates to a method for controlling a touch pad, comprising an object locate mode for locating an object on the touch pad comprising steps of: determining a measurement of capacitance of each of the pairs of electrodes of the touch pad, each pair comprising a row electrode and a column electrode transverse to the row electrode, comparing each measurement with a first detection threshold, and if the comparison of at least one measurement with the first threshold reveals the presence of an object on the touch pad, locating the object on the touch pad according to the capacitance measurements, the method comprising a proximity detection mode comprising steps of: determining a measurement representative of the capacitance between one or two electrodes and one or two other electrodes of the touch pad, and comparing a measurement obtained with a second detection threshold different from the first threshold.

Abstract translation: 本公开涉及一种用于控制触摸板的方法，包括用于在触摸板上定位对象的对象定位模式，包括以下步骤：确定触摸板的每对电极的电容的测量，每对包括 与行电极横向的行电极和列电极，将每个测量与第一检测阈值进行比较，并且如果至少一个测量与第一阈值的比较显示在触摸板上存在对象，则将对象定位在 所述触摸板根据所述电容测量，所述方法包括接近检测模式，包括以下步骤：确定代表所述触摸板的一个或两个电极与所述一个或两个其他电极之间的电容的测量值，以及将所获得的测量结果与 第二检测阈值与第一阈值不同。

公开(公告)号：US20150097630A1

公开(公告)日：2015-04-09

申请号：US14502095

申请日：2014-09-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Bruno Gailhard ,  Michel Cuenca

IPC: H03L1/02 ,  H03K19/0948 ,  H03B5/04 ,  H03K19/017

CPC classification number: H03L1/026 ,  G05F3/262 ,  G11C7/04 ,  H03B5/04 ,  H03K19/00323 ,  H03K19/00369 ,  H03K19/0948

Abstract: A method includes generation of a first current proportional to absolute temperature and formation of a second current representative of the temperature variation of the threshold voltages of the transistors of the inverter and limited to a fraction of the first current. This fraction is less than one. The inverter is supplied with a supply current equal to the first current minus the limited second current.

Abstract translation: 一种方法包括产生与绝对温度成比例的第一电流和形成表示逆变器的晶体管的阈值电压的温度变化的第二电流，并将其限制为第一电流的一部分。 这个比例小于1。 逆变器的供电电流等于第一电流减去受限的第二电流。

公开(公告)号：US08940604B2

公开(公告)日：2015-01-27

申请号：US13786197

申请日：2013-03-05

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa

IPC: H01L21/336 ,  H01L29/788 ,  H01L29/66 ,  G11C16/04 ,  H01L27/115 ,  G11C16/10 ,  G11C16/16

CPC classification number: H01L29/788 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/16 ,  H01L27/11524 ,  H01L29/66825

Abstract: The disclosure relates to an integrated circuit comprising a nonvolatile memory on a semiconductor substrate. The integrated circuit comprises a doped isolation layer implanted in the depth of the substrate, isolated conductive trenches reaching the isolation layer and forming gates of selection transistors of memory cells, isolation trenches perpendicular to the conductive trenches and reaching the isolation layer, and conductive lines parallel to the conductive trenches, extending on the substrate and forming control gates of charge accumulation transistors of memory cells. The isolation trenches and the isolated conductive trenches delimit a plurality of mini wells in the substrate, the mini wells electrically isolated from each other, each having a floating electrical potential and comprising two memory cells.

Abstract translation: 本公开涉及一种在半导体衬底上包括非易失性存储器的集成电路。 集成电路包括注入衬底深度的掺杂隔离层，隔离的导电沟槽到达隔离层并形成存储单元的选择晶体管的栅极，垂直于导电沟槽并到达隔离层的隔离沟槽，并且导线平行 到导电沟槽，在衬底上延伸并形成存储器单元的电荷累积晶体管的控制栅极。 隔离沟槽和隔离的导电沟槽限定了衬底中的多个微型阱，所述微型阱彼此电隔离，每个具有浮置电势并且包括两个存储单元。