公开(公告)号：US12125874B2

公开(公告)日：2024-10-22

申请号：US17647481

申请日：2022-01-10

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Kyoungyoon Baek

IPC: H01L23/522 ,  H01L49/02 ,  H10B12/00

CPC classification number: H01L28/92

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure, and a semiconductor structure. The method of manufacturing a semiconductor structure includes: providing an initial structure, wherein the initial structure includes a substrate, a laminated structure, and capacitor units, and the laminated structure includes support layers; forming a first mask layer, wherein the first mask layer covers a top surface of the laminated structure; forming a first opening in the first mask layer, wherein the first opening exposes the top surface of the laminated structure, and a projection region of the first opening on the substrate at least partially overlaps with projection regions of the capacitor units on the substrate; forming a shielding structure, wherein the shielding structure is located in the first opening, and the shielding structure covers a sidewall of the first opening.

公开(公告)号：US12125749B2

公开(公告)日：2024-10-22

申请号：US17479146

申请日：2021-09-20

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Yuanhao Gao

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/532

CPC classification number: H01L21/76898 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/481 ,  H01L23/53238

Abstract: Embodiments of this application provide a semiconductor structure and a method for forming the same. The method for forming the semiconductor structure includes: a first substrate is provided; the back surface of the first substrate is etched to form a trench; a conductive layer is formed in the trench; a first conductive column that extends into the trench is formed at a back surface of the first substrate; a device layer is formed at a front surface of the first substrate, and the device layer includes a storage array and a contact structure; and a second conductive column that penetrates through the device layer and extends into the first substrate is formed; the first conductive column is electrically connected with the second conductive column through the conductive layer.

公开(公告)号：US12125704B2

公开(公告)日：2024-10-22

申请号：US17647766

申请日：2022-01-12

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Qiang Wan ,  Jun Xia ,  Kangshu Zhan ,  Penghui Xu ,  Tao Liu ,  Sen Li

IPC: H01L21/033

CPC classification number: H01L21/0338 ,  H01L21/0335 ,  H01L21/0337

Abstract: A method for forming a pattern can include the following operations. A substrate is provided, on the surface of which a patterned photoresist layer is formed. Based on the photoresist layer, isolation sidewalls are formed, in which each isolation sidewall includes a first sidewall close to the photoresist layer and a second sidewall away from the photoresist layer. Core material layers are formed between two adjacent isolation sidewalls. The second sidewalls are removed to form the pattern composed of the first sidewalls and the core material layers.

公开(公告)号：US12122014B2

公开(公告)日：2024-10-22

申请号：US17443538

申请日：2021-07-27

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Jinwei Dang ,  Chin-Chung Ku ,  Lingfeng Han

IPC: B24B37/34 ,  B24B37/04

CPC classification number: B24B37/34 ,  B24B37/042

Abstract: The replacing tool includes a first beam, a connection mechanism, a second beam, a first hook, and a second hook. The first beam is connected to the second beam through the connection mechanism. The first hook is fixedly connected to the first beam, and a portion of the first hook is configured to be engaged into a concave end of the sponge brush. The second hook is fixedly connected to the second beam, and a portion of the second hook is arranged around a convex end of the sponge brush. The first beam and the second beam are movable relative to each other, so that the first hook is engaged with or detached from the concave end of the sponge brush and the second hook is engaged with or detached from the convex end of the sponge brush.

公开(公告)号：US12119315B2

公开(公告)日：2024-10-15

申请号：US17650851

申请日：2022-02-13

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Chih-Wei Chang

IPC: H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L24/05 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/03 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L2224/03622 ,  H01L2224/05009 ,  H01L2224/05011 ,  H01L2224/05014 ,  H01L2224/05015 ,  H01L2224/05017 ,  H01L2224/05073 ,  H01L2224/0801 ,  H01L2224/08055 ,  H01L2224/08056 ,  H01L2224/08059 ,  H01L2224/0807 ,  H01L2224/08147 ,  H01L2224/08148 ,  H01L2224/80895 ,  H01L2225/06524 ,  H01L2225/06544 ,  H01L2225/06548

Abstract: A chip bonding method includes the following operations. A first chip is provided, which includes a first contact pad including a first portion lower than a first surface of a first substrate and a second portion higher than the first surface of the first substrate to form the stepped first contact pad. A second chip is provided, which includes a second contact pad including a third portion lower than a third surface of a second substrate and a fourth portion higher than the third surface of the second substrate to form the stepped second contact pad. The first chip and the second chip are bonded. The first portion of the first chip contacts with the fourth portion of the second chip, and the second portion of the first chip contacts with the third portion of the second chip.

公开(公告)号：US12119286B2

公开(公告)日：2024-10-15

申请号：US17647883

申请日：2022-01-13

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： ChihCheng Liu

IPC: H01L21/00 ,  H01L21/768 ,  H01L23/48 ,  H01L23/528 ,  H01L23/532 ,  H01L25/065

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/53257 ,  H01L25/0657 ,  H01L2225/06541

Abstract: A die, a memory and a method of manufacturing the die are provided. The die includes a substrate and a conductive structure, where the substrate has an interconnection structure layer, the conductive structure includes a first conductive structure and a second conductive structure connected with the first conductive structure, the first conductive structure is connected with the interconnection structure layer, and a coefficient of thermal expansion of the first conductive structure is smaller than that of copper.

公开(公告)号：US12119083B2

公开(公告)日：2024-10-15

申请号：US17874813

申请日：2022-07-27

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Shuhao Zhang ,  Ning Li

IPC: G11C11/08 ,  G11C7/10 ,  G11C7/12 ,  G11C8/08 ,  G11C11/408 ,  G11C11/4096 ,  H03K3/356

CPC classification number: G11C8/08 ,  G11C7/1096 ,  G11C7/12 ,  G11C11/4085 ,  G11C11/4096 ,  H03K3/356113

Abstract: A drive circuit, a method for driving the drive circuit and a memory are provided. The drive circuit includes a word line drive circuit and a first control circuit. The word line drive circuit includes an input terminal, an output terminal and at least one N-type transistor. The word line drive circuit is configured to provide an output signal to the output terminal according to an input signal received by the input terminal. The first control circuit is configured to pull down, in response to the input signal being a first control signal, a voltage of a substrate terminal of the at least one N-type transistor in the word line drive circuit, to reduce a leakage current of the at least one N-type transistor.

公开(公告)号：US12114485B2

公开(公告)日：2024-10-08

申请号：US17669573

申请日：2022-02-11

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Qinghua Han

IPC: H10B12/00 ,  H01L29/10 ,  H01L29/423 ,  H01L29/786

CPC classification number: H10B12/482 ,  H01L29/1041 ,  H01L29/42392 ,  H01L29/78696 ,  H10B12/30 ,  H10B12/488

Abstract: Provided are a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes: a base; a bit line; and a semiconductor channel including a first doped region, a channel region, and a second doped region that are sequentially arranged, where the first doped region contacts the bit line, and the first doped region, the channel region, and the second doped region are doped with first-type doped ions. The channel region is further doped with second-type doped ions, enabling a concentration of majority carriers in the channel region to be less than a concentration of majority carriers in the first doped region and a concentration of majority carriers in the second doped region. The first-type doped ions are one of N-type ions or P-type ions, and the second-type doped ions are the other of N-type ions or P-type ions.

公开(公告)号：US12114483B2

公开(公告)日：2024-10-08

申请号：US17605011

申请日：2021-07-28

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Dandan He

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/02

Abstract: The present application provides a method for manufacturing a semiconductor device, and a semiconductor device. The method includes: providing a substrate; forming a first conductive material layer on the substrate; performing plasma treatment on the first conductive material layer to form a first conductive layer; successively forming a second conductive layer, a first block layer, a third conductive layer and a fourth conductive layer on the first conductive layer; forming a dielectric layer on the fourth conductive layer, and forming an ohmic contact layer at a junction of the first conductive layer and the second conductive layer; forming an initial bit line structure; performing NH3/N2 plasma treatment on the initial bit line structure to form a second block layer on a sidewall of the first conductive layer and a third block layer on a sidewall of the ohmic contact layer.

公开(公告)号：US12113531B2

公开(公告)日：2024-10-08

申请号：US18155759

申请日：2023-01-18

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Yingdong Guo ,  Jing Xu ,  Wei Jiang ,  Xue Shan

IPC: H03K21/02 ,  H05K1/02 ,  H04B1/04

CPC classification number: H03K21/02 ,  H05K1/0296 ,  H04B1/04

Abstract: A layout structure and a method for fabricating the same. A frequency divider pattern layer includes a first frequency divider region, a second frequency divider region, a third frequency divider region and a fourth frequency divider region arranged centrosymmetrically. A conductor pattern layer includes a first sub-conductor pattern layer and a second sub-conductor pattern layer stacked. The first sub-conductor pattern layer is configured to communicate the first frequency divider region with the second frequency divider region, and communicate the third frequency divider region with the fourth frequency divider region. The second sub-conductor pattern layer is configured to communicate the first frequency divider region with the fourth frequency divider region, and communicate the second frequency divider region with the third frequency divider region. The embodiments reduce a channel transmission difference between different frequency dividers in a frequency divider structure.