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    System and method for routing in an electronic circuit design
    51.
    发明授权
    System and method for routing in an electronic circuit design 有权

    公开(公告)号：US11373027B1

    公开(公告)日：2022-06-28

    申请号：US17194589

    申请日：2021-03-08

    Applicant: Cadence Design Systems, Inc.

    Inventor： Laurent Rene Saint-Marcel

    IPC: G06F30/394 ,  G06F30/12

    Abstract: The present disclosure relates to a method for use with an electronic design. Embodiments may include receiving, at a graphical user interface, an indication of a desired wire creation associated with an electronic design and determining a plurality of routing solutions, based upon, at least in part, the desired wire creation. Embodiments may further include simultaneously displaying the plurality of routing solutions at the graphical user interface, wherein a predicted preferred routing solution is graphically emphasized. Embodiments may also include receiving a selection from a user, at the graphical user interface, of one of the plurality of routing solutions and storing the selection for subsequent use.

    System, method, and computer-program product for routing in an electronic design using deep learning
    52.
    发明授权
    System, method, and computer-program product for routing in an electronic design using deep learning 有权

    公开(公告)号：US11348000B1

    公开(公告)日：2022-05-31

    申请号：US15377389

    申请日：2016-12-13

    Applicant: Cadence Design Systems, Inc.

    Inventor： Weibin Ding ,  Jie Chen

    IPC: G06N3/08 ,  G06F30/00

    Abstract: The present disclosure relates to a computer-implemented method for routing in an electronic design. Embodiments may include receiving, using at least one processor, global route data associated with an electronic design as an input and generating detail route data, based upon, at least in part, the global route data. Embodiments may further include transforming one or more of the detail route data and the global route data into at least one input feature and at least one output result of a deep neural network. Embodiments may also include training the deep neural network with the global route data and the detail route data and predicting an output associated with a detail route based upon, at least in part, a trained deep neural network model. Embodiments may also include generating routing information for each routing grid.

    Differential clock generator circuit
    54.
    发明授权
    Differential clock generator circuit 有权

    公开(公告)号：US11294416B1

    公开(公告)日：2022-04-05

    申请号：US17167707

    申请日：2021-02-04

    Applicant: Cadence Design Systems, Inc.

    Inventor： Steven Elliott Mikes

    IPC: G06F1/06 ,  H03K17/687 ,  H03K19/20

    Abstract: A circuit can include a non-inverter circuit configured to generate a first clock signal with a first logic state during a first period of time in response to an input clock signal having the first logic state, and with a second logic state during a second period of time in response to the input clock signal having the second logic state. The circuit can include an inverter circuit that can be configured to generate a second clock signal with the second logic state during the first period of time in response to the input clock signal having the first logic state, and with the second logic state during the second period of time in response to the input clock signal having the second logic state.

    Method and system for functional safety verification using fault relation rules
    55.
    发明授权
    Method and system for functional safety verification using fault relation rules 有权

    公开(公告)号：US11216606B1

    公开(公告)日：2022-01-04

    申请号：US16942801

    申请日：2020-07-30

    Applicant: Cadence Design Systems, Inc.

    Inventor： Ophir Turbovich ,  Muhammad Zoabi ,  Yuval Shpak

    IPC: G06F30/3308 ,  G06F119/02 ,  G06F117/04

    Abstract: A computer implemented method for functional safety verification includes simulating SA0 and/or SA1 faults at a Q output port of each sequential element in a first representation of an electronic design, to determine whether any of the simulated faults is detectable by a safety mechanism, determining, based on one or more fault relation rules and based on a second gate-level representation of the electronic design, whether any of the faults is also detectable by the safety mechanism if occurred at one or more input ports of the respective sequential element or one or more input ports of a clockgate of the respective sequential element, and identifying a remainder of input ports and input ports of a clockgate of each of the sequential elements at which the faults are not determined to be detectable by the safety mechanism based on the one or a plurality of fault relation rules.

    Data alignment in physical layer device
    57.
    发明授权
    Data alignment in physical layer device 有权

    公开(公告)号：US11190331B1

    公开(公告)日：2021-11-30

    申请号：US17124280

    申请日：2020-12-16

    Applicant: Cadence Design Systems, Inc.

    Inventor： Loren B. Reiss ,  Scott David Huss ,  Fred Staples Stivers ,  James Dennis Vandersand, Jr.

    IPC: H04L7/00

    Abstract: A physical layer (PHY) device comprises a phase interpolator to generate a set of sampler clocks. A sampler of the PHY device samples a calibration data pattern based on the set of sampler clocks. A data alignment system of the PHY device performs a coarse calibration and a fine calibration on the sampler clock signals. During the coarse calibration, the data alignment system moves the sampler clock signals earlier or later in time relative to the sampled data based on a first bit of the sampled data. During the fine calibration, the data alignment system moves the sampler clock signals earlier or later in time relative to the sampled data based on the first bit, a second bit, and a third bit in the sampled data.

    Inline hardware compression subsystem for emulation trace data
    60.
    发明授权
    Inline hardware compression subsystem for emulation trace data 有权

    公开(公告)号：US11176018B1

    公开(公告)日：2021-11-16

    申请号：US16219836

    申请日：2018-12-13

    Applicant: CADENCE DESIGN SYSTEMS, INC.

    Inventor： Aruna Aluri ,  Linwei Ding ,  Mitchell G. Poplack

    IPC: G06F11/00 ,  G06F11/34 ,  G06F11/36 ,  G06F11/07 ,  G06F30/331

    Abstract: A trace subsystem of an emulation system may generate differential frame data based upon successive frames. If one compression mode, the trace subsystem may set a flag bit and store differential frame data if there is at least one non-zero bit in the differential frame data. If the differential frame data includes only zero bits, the trace subsystem may set the flag bit without storing the frame data. In another compression mode, the computer may further compress the differential data if the frame data includes one (one-hot) or two (two-hot) non-zero bits. The controller may set flag bits to indicate one of all-zeroes, one-hot, two-hot, and random data conditions (more than two non-zero bits). For one-hot or two-hot conditions, the controller may store bits indicating the positions of the non-zero bits. For random data conditions, the controller may store the entire differential frame.

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