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    APPARATUS AND METHOD FOR FORCIBLY SHUTTING DOWN SYSTEM
    53.
    发明申请
    APPARATUS AND METHOD FOR FORCIBLY SHUTTING DOWN SYSTEM 有权
    装置和方法，用于强制切断系统

    公开(公告)号：US20090313487A1

    公开(公告)日：2009-12-17

    申请号：US12370701

    申请日：2009-02-13

    Applicant: Jung-Hwan LEE

    Inventor： Jung-Hwan LEE

    IPC: G06F1/00

    CPC classification number: G06F1/3203 ,  G06F1/3246 ,  Y02D50/20

    Abstract: The present invention relates to an apparatus and method for forcibly shutting down a computer system, and more specifically, to an apparatus and method for forcibly shutting down a system when the system is determined to be in an abnormal state. An apparatus for forcibly shutting down a system according to a specific embodiment of the present invention comprises a reception unit 10 for receiving a power management control signal; a power state detection unit 20 for detecting a current power state of the system; a determination unit 30 for determining whether a system execution state is normal by comparing the power management control signal received by the reception unit 10 and a detection result of the power state detection unit 20; and a forced-shutdown unit 40 for forcibly shutting down the system when the system execution state is determined to be abnormal by the determination unit 30. According to the present invention so configured, there are advantages in that when an error occurs in a computer system and the system operation is inadvertently suspended while the system is not shut down, the system is forcibly shut down, whereby continuous consumption of battery power can be prevented, and danger of accident occurring due to an increase in battery temperature can be prevented.

    Abstract translation: 本发明涉及一种用于强制关闭计算机系统的装置和方法，更具体地说，涉及一种当系统被确定处于异常状态时强制关闭系统的装置和方法。 根据本发明的具体实施例的用于强制关闭系统的装置包括：接收单元10，用于接收功率管理控制信号; 功率状态检测单元20，用于检测系统的当前功率状态; 确定单元30，用于通过比较由接收单元10接收的功率管理控制信号和功率状态检测单元20的检测结果来确定系统执行状态是否正常; 以及强制关闭单元40，用于当确定单元30确定系统执行状态为异常时强制关闭系统。根据如此配置的本发明，具有如下优点：当在计算机系统中发生错误时 并且在系统不关闭的情况下系统操作无意中断，系统被强制关闭，从而可以防止电池电力的持续消耗，并且可以防止由于电池温度升高而引起的事故危险。

    ENHANCED-ACCURACY BATTERY CAPACITY PREDICTION
    55.
    发明申请
    ENHANCED-ACCURACY BATTERY CAPACITY PREDICTION 失效
    增强精度电池容量预测

    公开(公告)号：US20080007221A1

    公开(公告)日：2008-01-10

    申请号：US11564387

    申请日：2006-11-29

    Applicant: Jung Hwan LEE

    Inventor： Jung Hwan LEE

    IPC: H02J7/00

    CPC classification number: G01R31/3648

    Abstract: Enhanced-accuracy battery capacity prediction in which a residual capacity of a battery associated with a mobile electronic device are determined and displayed. One or more characteristic values of the battery are detected and an appropriate battery discharge curve is selected from multiple stored battery discharge curves based on the electrical current supply rate or a number of historical charge/discharge cycles of the battery, or both. A detected battery voltage is compared to the selected curve, and the residual capacity of the battery is calculated based on the present discharge capacity and the useful discharge capacity of the battery based on the selected curve. The residual capacity accurately reflects the present operational state of the device and the present state of the battery. The accurate residual capacity of the battery is displayed on a display device for user viewing.

    Abstract translation: 确定并显示与移动电子设备相关联的电池的剩余容量的增强精度的电池容量预测。 检测电池的一个或多个特征值，并且基于电流供给速率或电池的历史充电/放电循环的数量，或两者，从多个存储的电池放电曲线中选择适当的电池放电曲线。 将检测到的电池电压与所选择的曲线进行比较，并且基于当前放电容量和基于所选曲线的电池的有用放电容量来计算电池的剩余容量。 剩余容量准确地反映了设备的当前操作状态和电池的当前状态。 电池的精确剩余容量显示在用于观看的显示装置上。

    Method of making semiconductor devices having ohmic contact
    56.
    发明授权
    Method of making semiconductor devices having ohmic contact 失效
    制造具有欧姆接触的半导体器件的方法

    公开(公告)号：US5013686A

    公开(公告)日：1991-05-07

    申请号：US252514

    申请日：1988-09-30

    Applicant: Kyu-Hyun Choi ,  Heyung-Sub Lee ,  Jung-Hwan Lee

    Inventor： Kyu-Hyun Choi ,  Heyung-Sub Lee ,  Jung-Hwan Lee

    IPC: H01L21/02 ,  H01L21/265 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8244 ,  H01L27/11 ,  H01L29/78

    CPC classification number: H01L28/20 ,  H01L21/28525 ,  H01L21/76877 ,  H01L27/1112 ,  Y10S148/019 ,  Y10S148/147

    Abstract: A method being capable of achieving the reduction in contact resistance between each layer when bringing a silicide layer into contact with a polycrystalline-silicon (polysilicon) layer in the manufacture of semiconductor devices. The method comprises the steps of forming a polysilicon layer and a silicide layer thereon over a partial top surface of a semiconductor substrate, forming an insulating layer over said silicide layer and the entire top surface of the substrate, forming a contact window by etching the partial area of the insulating layer over said silicide layer, and forming a polysilicon layer over the entire top surface of the substrate after performing ion-implantation through said contact window, wherein said ion-implantation is performed with N-type high doping into the silicide.

    Abstract translation: 一种在半导体器件的制造中使硅化物层与多晶硅（多晶硅）层接触时能够实现各层之间的接触电阻降低的方法。 该方法包括以下步骤：在半导体衬底的部分顶表面上形成多晶硅层和硅化物层，在所述硅化物层和衬底的整个顶表面上形成绝缘层，通过蚀刻部分 在所述硅化物层上的绝缘层的面积，以及在通过所述接触窗进行离子注入之后，在所述衬底的整个顶表面上形成多晶硅层，其中所述离子注入在所述硅化物中进行N型高掺杂。

    Gas injection apparatus and substrate processing apparatus using same
    58.
    发明授权
    Gas injection apparatus and substrate processing apparatus using same 有权

    公开(公告)号：US09732424B2

    公开(公告)日：2017-08-15

    申请号：US13393498

    申请日：2010-08-24

    Applicant: Jung-Hwan Lee ,  Woo-Young Park ,  Tae-Ho Hahm

    Inventor： Jung-Hwan Lee ,  Woo-Young Park ,  Tae-Ho Hahm

    IPC: C23C16/455 ,  H01L21/687

    CPC classification number: C23C16/45551 ,  C23C16/45565 ,  C23C16/45574 ,  H01L21/68764 ,  H01L21/68771

    Abstract: Provided are a gas injection device and substrate processing apparatus using the same. The gas injection device includes a plurality of gas injection units disposed above a substrate support part rotatably disposed within a chamber to support a plurality of substrates, the plurality of gas injection units being disposed along a circumference direction with respect to a center point of the substrate support part to inject a process gas onto the substrates. Wherein each of the plurality of gas injection units includes a top plate in which an inlet configured to introduce the process gas is provided and an injection plate disposed under the top plate to define a gas diffusion space between the injection plate and the top plate along a radius direction of the substrate support part, the injection plate having a plurality of gas injection holes under the gas diffusion space to inject the process gas introduced through the inlet and diffused in the gas diffusion space onto the substrate. In at least one gas injection unit of the plurality of gas injection units, the process gas is introduced into the gas diffusion space at a plurality of points.

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE
    60.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE 有权
    三维半导体存储器件

    公开(公告)号：US20170062330A1

    公开(公告)日：2017-03-02

    申请号：US15201994

    申请日：2016-07-05

    Applicant: Jeeyong KIM ,  Daeseok BYEON ,  Jung-Hwan LEE ,  Sanghoon AHN

    Inventor： Jeeyong KIM ,  Daeseok BYEON ,  Jung-Hwan LEE ,  Sanghoon AHN

    IPC: H01L23/522 ,  H01L23/528 ,  H01L27/115

    CPC classification number: H01L23/5226 ,  H01L21/7682 ,  H01L23/528 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2221/1047

    Abstract: Three-dimensional (3D) semiconductor memory devices capable of improving reliability may be provided. For example, a three dimensional (3D) memory device, in which a plurality of memory cell strings are vertically arranged, may include a substrate, a stack structure of alternating a plurality of interlayer dielectric (ILD) layers and a plurality of gate electrodes, at least one of the ILD layers including pores, a vertical structure penetrating the stack structure and electrically connected to the substrate, and a data storage layer between the stack structure and the vertical structure.

    Abstract translation: 可以提供能够提高可靠性的三维（3D）半导体存储器件。 例如，其中垂直排列有多个存储单元串的三维（3D）存储器件可以包括衬底，交替多个层间电介质层（ILD）层和多个栅电极的堆叠结构， ILD层中的至少一个包括孔，穿过堆叠结构并电连接到衬底的垂直结构，以及堆叠结构和垂直结构之间的数据存储层。

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