公开(公告)号：US20070287255A1

公开(公告)日：2007-12-13

申请号：US11452883

申请日：2006-06-13

Applicant: Brian S. Doyle ,  Uday Shah ,  Been-Yih Jin ,  Jack T. Kavalieros

Inventor： Brian S. Doyle ,  Uday Shah ,  Been-Yih Jin ,  Jack T. Kavalieros

IPC: H01L21/336

CPC classification number: H01L29/7851 ,  H01L29/66795

Abstract: Embodiments of the invention include apparatuses and methods relating to three dimensional transistors having high-k dielectrics and metal gates with fins protected by a hard mask layer on their top surface. In one embodiment, the hard mask layer includes an oxide.

Abstract translation: 本发明的实施例包括与具有高k电介质的三维晶体管和金属栅极相关的装置和方法，其翅​​片由其顶表面上的硬掩模层保护。 在一个实施例中，硬掩模层包括氧化物。

公开(公告)号：US20070232078A1

公开(公告)日：2007-10-04

申请号：US11395853

申请日：2006-03-31

Applicant: Matthew V. Metz ,  Suman Datta ,  Mark L. Doczy ,  Jack T. Kavalieros ,  Robert S. Chau ,  Gilbert Dewey

Inventor： Matthew V. Metz ,  Suman Datta ,  Mark L. Doczy ,  Jack T. Kavalieros ,  Robert S. Chau ,  Gilbert Dewey

IPC: H01L21/31

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L29/513 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method including depositing a material for a gate electrode on a substrate over a dielectric material, the gate electrode material comprising a metal; depositing a capping material over the gate electrode material under processing conditions that will not promote any oxygen species associated with the gate electrode material to travel through the gate electrode material to the substrate; and patterning a gate electrode structure comprising the gate electrode material.

Abstract translation: 一种方法，包括在电介质材料上的衬底上沉积用于栅电极的材料，所述栅电极材料包括金属; 在不会促使与栅电极材料相关联的任何氧物质通过栅极电极材料移动到衬底的加工条件下，在栅电极材料上沉积封盖材料; 以及图案化包括栅电极材料的栅电极结构。

公开(公告)号：US20200098932A1

公开(公告)日：2020-03-26

申请号：US16142300

申请日：2018-09-26

Applicant: Travis W. LAJOIE ,  Abhishek SHARMA ,  Van H. LE ,  Chieh-Jen KU ,  Pei-Hua WANG ,  Jack T. KAVALIEROS ,  Bernhard SELL ,  Tahir GHANI ,  Juan ALZATE VINASCO

Inventor： Travis W. LAJOIE ,  Abhishek SHARMA ,  Van H. LE ,  Chieh-Jen KU ,  Pei-Hua WANG ,  Jack T. KAVALIEROS ,  Bernhard SELL ,  Tahir GHANI ,  Juan ALZATE VINASCO

IPC: H01L29/786 ,  H01L29/49 ,  H01L29/66 ,  H01L27/108

Abstract: Embodiments herein describe techniques for a semiconductor device including a capacitor and a transistor above the capacitor. A contact electrode may be shared between the capacitor and the transistor. The capacitor includes a first plate above a substrate, and the shared contact electrode above the first plate and separated from the first plate by a capacitor dielectric layer, where the shared contact electrode acts as a second plate for the capacitor. The transistor includes a gate electrode above the substrate and above the capacitor; a channel layer separated from the gate electrode by a gate dielectric layer, and in contact with the shared contact electrode; and a source electrode above the channel layer, separated from the gate electrode by the gate dielectric layer, and in contact with the channel layer. The shared contact electrode acts as a drain electrode of the transistor. Other embodiments may be described and/or claimed.

公开(公告)号：US20200091274A1

公开(公告)日：2020-03-19

申请号：US16134876

申请日：2018-09-18

Applicant: Abhishek SHARMA ,  Ravi PILLARISETTY ,  Brian DOYLE ,  Elijah KARPOV ,  Prashant MAJHI ,  Gilbert DEWEY ,  Benjamin CHU-KUNG ,  Van H. LE ,  Jack T. KAVALIEROS ,  Tahir GHANI

Inventor： Abhishek SHARMA ,  Ravi PILLARISETTY ,  Brian DOYLE ,  Elijah KARPOV ,  Prashant MAJHI ,  Gilbert DEWEY ,  Benjamin CHU-KUNG ,  Van H. LE ,  Jack T. KAVALIEROS ,  Tahir GHANI

IPC: H01L49/02 ,  H01L29/51 ,  H01L29/66

Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT), which may include a substrate and a transistor above the substrate. The transistor includes a channel layer above the substrate, a gate dielectric layer adjacent to the channel layer, and a gate electrode separated from the channel layer by the gate dielectric layer. The gate dielectric layer includes a non-linear gate dielectric material. The gate electrode, the channel layer, and the gate dielectric layer form a non-linear capacitor. Other embodiments may be described and/or claimed.

公开(公告)号：US20180013000A1

公开(公告)日：2018-01-11

申请号：US15528763

申请日：2014-12-24

Applicant: Willy Rachmady ,  Matthew V. Metz ,  Chandra S. Mohapatra ,  Gilbert Dewey ,  Nadia M. Rahhal-Orabi ,  Tahir Ghani ,  Anand S. Murthy ,  Jack T. Kavalieros ,  Glenn A. Glass

Inventor： Willy Rachmady ,  Matthew V. Metz ,  Chandra S. Mohapatra ,  Gilbert Dewey ,  Nadia M. Rahhal-Orabi ,  Tahir Ghani ,  Anand S. Murthy ,  Jack T. Kavalieros ,  Glenn A. Glass

IPC: H01L29/78 ,  H01L21/762 ,  H01L21/02 ,  H01L21/306 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/7853 ,  H01L21/02532 ,  H01L21/02694 ,  H01L21/30625 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78696

Abstract: An embodiment includes a microelectronic device comprising: a substrate comprising a raised portion and a non-raised portion, wherein a dielectric material is disposed adjacent the raised portion, an epitaxial sub-fin structure disposed on the raised portion, wherein a bottom portion of the epitaxial sub-fin structure comprises an asymmetric profile, and an epitaxial fin device structure disposed on the sub-fin structure. Other embodiments are described herein.

公开(公告)号：US09608055B2

公开(公告)日：2017-03-28

申请号：US13996502

申请日：2011-12-23

Applicant: Willy Rachmady ,  Van H. Le ,  Ravi Pillarisetty ,  Jack T. Kavalieros ,  Robert S. Chau ,  Harold W. Kennel

Inventor： Willy Rachmady ,  Van H. Le ,  Ravi Pillarisetty ,  Jack T. Kavalieros ,  Robert S. Chau ,  Harold W. Kennel

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/778 ,  H01L29/10 ,  H01L29/786 ,  H01L21/28 ,  H01L29/165 ,  H01L29/78 ,  B82Y10/00

CPC classification number: H01L29/1083 ,  B82Y10/00 ,  H01L21/28255 ,  H01L29/0603 ,  H01L29/0607 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66431 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7781 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78603 ,  H01L29/78684 ,  H01L29/78696

Abstract: Semiconductor devices having germanium active layers with underlying diffusion barrier layers are described. For example, a semiconductor device includes a gate electrode stack disposed above a substrate. A germanium active layer is disposed above the substrate, underneath the gate electrode stack. A diffusion barrier layer is disposed above the substrate, below the germanium active layer. A junction leakage suppression layer is disposed above the substrate, below the diffusion barrier layer. Source and drain regions are disposed above the junction leakage suppression layer, on either side of the gate electrode stack.

公开(公告)号：US09443936B2

公开(公告)日：2016-09-13

申请号：US13870184

申请日：2013-04-25

Applicant: Prashant Majhi ,  Mantu K. Hudait ,  Jack T. Kavalieros ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Titash Rakshit ,  Willman Tsai

Inventor： Prashant Majhi ,  Mantu K. Hudait ,  Jack T. Kavalieros ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Titash Rakshit ,  Willman Tsai

IPC: H01L29/15 ,  H01L21/285 ,  H01L21/768 ,  H01L29/417 ,  H01L29/66 ,  H01L29/778 ,  H01L29/78 ,  H01L29/80 ,  H01L29/165 ,  H01L29/51

CPC classification number: H01L29/66431 ,  H01L21/28518 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76897 ,  H01L29/152 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7848 ,  H01L29/802

Abstract: Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well.

Abstract translation: 所描述的实施例包括具有金属源/漏极的应变晶体管量子阱（QW）沟道区，以及保形再生长源/漏极，以在MOS沟道区中赋予单轴应变。 沟道层的去除部分可以填充具有不同于沟道材料的晶格间隔的结合材料，以在通道中引起单轴应变，以及在沟道层中引起的双轴应变 顶部阻挡层和量子阱的底部缓冲层。

公开(公告)号：US09419140B2

公开(公告)日：2016-08-16

申请号：US14882440

申请日：2015-10-13

Applicant: Jack T. Kavalieros ,  Nancy Zelick ,  Been-Yih Jin ,  Markus Kuhn ,  Stephen M. Cea

Inventor： Jack T. Kavalieros ,  Nancy Zelick ,  Been-Yih Jin ,  Markus Kuhn ,  Stephen M. Cea

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/165

CPC classification number: H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7842 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7854

Abstract: Techniques are disclosed for enabling multi-sided condensation of semiconductor fins. The techniques can be employed, for instance, in fabricating fin-based transistors. In one example case, a strain layer is provided on a bulk substrate. The strain layer is associated with a critical thickness that is dependent on a component of the strain layer, and the strain layer has a thickness lower than or equal to the critical thickness. A fin is formed in the substrate and strain layer, such that the fin includes a substrate portion and a strain layer portion. The fin is oxidized to condense the strain layer portion of the fin, so that a concentration of the component in the strain layer changes from a pre-condensation concentration to a higher post-condensation concentration, thereby causing the critical thickness to be exceeded.

公开(公告)号：US20160204037A1

公开(公告)日：2016-07-14

申请号：US14777736

申请日：2013-06-28

Applicant: Niti Goel ,  Ravi Pillarisetty ,  Willy Rachmady ,  Jack T. Kavalieros ,  Gilbert Dewey ,  Benjamin Chu-Kung ,  Marko Radosavljevic ,  Matthew V. Metz ,  Niloy Mukherjee ,  Robert S. Chau

Inventor： Niti Goel ,  Ravi Pillarisetty ,  Willy Rachmady ,  Jack T. Kavalieros ,  Gilbert Dewey ,  Benjamin Chu-Kung ,  Marko Radosavljevic ,  Matthew V. Metz ,  Niloy Mukherjee ,  Robert S. Chau

IPC: H01L21/8238 ,  H01L21/762 ,  H01L21/02

CPC classification number: H01L21/823807 ,  H01L21/0245 ,  H01L21/02455 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/267 ,  H01L29/66795

Abstract: Different n- and p-types of device fins are formed by epitaxially growing first epitaxial regions of a first type material from a substrate surface at a bottom of first trenches formed between shallow trench isolation (STI) regions. The STI regions and first trench heights are at least 1.5 times their width. The STI regions are etched away to expose the top surface of the substrate to form second trenches between the first epitaxial regions. A layer of a spacer material is formed in the second trenches on sidewalls of the first epitaxial regions. Second epitaxial regions of a second type material are grown from the substrate surface at a bottom of the second trenches between the first epitaxial regions. Pairs of n- and p-type fins can be formed from the first and second epitaxial regions. The fins are co-integrated and have reduced defects from material interface lattice mismatch.

Abstract translation: 通过从在浅沟槽隔离（STI）区域之间形成的第一沟槽的底部的衬底表面外延生长第一类型材料的第一外延区域，形成不同的n型和p型器件鳍。 STI区域和第​​一沟槽高度至少是其宽度的1.5倍。 蚀刻掉STI区域以暴露衬底的顶表面以在第一外延区域之间形成第二沟槽。 在第一外延区域的侧壁上的第二沟槽中形成间隔材料层。 在第二外延区域之间的第二沟槽的底部的衬底表面生长第二类型材料的第二外延区域。 可以从第一和第二外延区域形成正对和p型翅片对。 翅片是共同整合的，并且从材料界面晶格失配减少缺陷。

公开(公告)号：US09159823B2

公开(公告)日：2015-10-13

申请号：US13977188

申请日：2011-12-09

Applicant: Van H. Le ,  Benjamin Chu-Kung ,  Harold Hal W. Kennel ,  Willy Rachmady ,  Ravi Pillarisetty ,  Jack T. Kavalieros

Inventor： Van H. Le ,  Benjamin Chu-Kung ,  Harold Hal W. Kennel ,  Willy Rachmady ,  Ravi Pillarisetty ,  Jack T. Kavalieros

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/786 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/0673 ,  H01L21/02532 ,  H01L21/283 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/161 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66431 ,  H01L29/66477 ,  H01L29/66651 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7842 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78681 ,  H01L29/78687 ,  H01L29/78696

Abstract: Transistor structures having channel regions comprising alternating layers of compressively and tensilely strained epitaxial materials are provided. The alternating epitaxial layers can form channel regions in single and multigate transistor structures. In alternate embodiments, one of the two alternating layers is selectively etched away to form nanoribbons or nanowires of the remaining material. The resulting strained nanoribbons or nanowires form the channel regions of transistor structures. Also provided are computing devices comprising transistors comprising channel regions comprised of alternating compressively and tensilely strained epitaxial layers and computing devices comprising transistors comprising channel regions comprised of strained nanoribbons or nanowires.

Abstract translation: 提供具有包括压缩和拉伸应变外延材料的交替层的沟道区的晶体管结构。 交替的外延层可以在单和多晶体管结构中形成沟道区。 在替代实施例中，两个交替层中的一个被选择性地蚀刻掉以形成剩余材料的纳米带或纳米线。 得到的应变纳米带或纳米线形成晶体管结构的沟道区。 还提供了包括晶体管的计算设备，所述晶体管包括由交替的压缩和拉伸应变外延层组成的沟道区，以及包括包含由应变纳米带或纳米线组成的沟道区的晶体管的计算器件。