公开(公告)号：US07098094B2

公开(公告)日：2006-08-29

申请号：US10734768

申请日：2003-12-12

申请人： Jiong-Ping Lu

发明人： Jiong-Ping Lu

IPC分类号： H01L21/8238 ,  H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/28097 ,  H01L21/823835

摘要： A capping layer (118) is used during an anneal to form fully silicided NiSi gate electrodes (120). The capping layer (118) comprises a material with an affinity for boron, such as TiN. The capping layer (118) serves as a boron trap that reduces the interface boron concentration for PMOS transistors without reducing the interface arsenic concentration for NMOS transistors.

摘要翻译： 在退火期间使用覆盖层（118）以形成完全硅化的NiSi栅电极（120）。 覆盖层（118）包括对硼具有亲和性的材料，例如TiN。 覆盖层（118）用作硼阱，其降低PMOS晶体管的界面硼浓度，而不降低NMOS晶体管的界面砷浓度。

公开(公告)号：US20050215055A1

公开(公告)日：2005-09-29

申请号：US10808168

申请日：2004-03-24

申请人： Haowen Bu ,  Jiong-Ping Lu ,  Shaofeng Yu ,  Ping Jiang ,  Clint Montgomery

发明人： Haowen Bu ,  Jiong-Ping Lu ,  Shaofeng Yu ,  Ping Jiang ,  Clint Montgomery

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L29/66507 ,  H01L21/28097 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/4975 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： The present invention provides a semiconductor device, a method of manufacture therefor, and a method for manufacturing an integrated circuit. The semiconductor device (100), among other possible elements, includes a silicided gate electrode (150) located over a substrate (110), the silicided gate electrode (150) having gate sidewall spacers (160) located on sidewalls thereof. The semiconductor device (100) further includes source/drain regions (170) located in the substrate (110) proximate the silicided gate electrode (150), and silicided source/drain regions (180) located in the source/drain regions (170) and at least partially under the gate sidewall spacers (160).

摘要翻译： 本发明提供一种半导体器件及其制造方法以及集成电路的制造方法。 除了其它可能的元件之外，半导体器件（100）包括位于衬底（110）上方的硅化栅电极（150），硅化栅电极（150）具有位于其侧壁上的栅极侧壁间隔物（160）。 半导体器件（100）还包括位于靠近硅化物栅电极（150）的衬底（110）中的源/漏区（170）和位于源/漏区（170）中的硅化源/漏区（180） 并且至少部分地在栅极侧壁间隔件（160）下方。

公开(公告)号：US06903000B2

公开(公告)日：2005-06-07

申请号：US10114778

申请日：2002-04-03

申请人： Jiong-Ping Lu ,  Qi-Zhong Hong ,  Tz-Cheng Chiu ,  Changming Jin ,  David Permana ,  Ting Tsui

发明人： Jiong-Ping Lu ,  Qi-Zhong Hong ,  Tz-Cheng Chiu ,  Changming Jin ,  David Permana ,  Ting Tsui

IPC分类号： H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76834 ,  H01L21/76877 ,  H01L21/76883

摘要： Disclosed is a system for fabricating a semiconductor device (100). An interconnect structure (110) is formed on the semiconductor device (100) and a cap (112) is deposited over the interconnect structure (110). The interconnect structure (110) is annealed with the overlying cap (112) in place. The cap (112) is then removed after the interconnect structure (110) is annealed.

摘要翻译： 公开了一种用于制造半导体器件（100）的系统。 互连结构（110）形成在半导体器件（100）上，并且帽（112）沉积在互连结构（110）上。 互连结构（110）与上覆盖（112）退火就位。 然后在互连结构（110）退火之后去除盖（112）。

公开(公告)号：US06641867B1

公开(公告)日：2003-11-04

申请号：US09276043

申请日：1999-03-25

申请人： Wei-Yung Hsu ,  Jiong-Ping Lu ,  August J. Fischer ,  Ming-Jang Hwang

发明人： Wei-Yung Hsu ,  Jiong-Ping Lu ,  August J. Fischer ,  Ming-Jang Hwang

IPC分类号： B05D512

CPC分类号： H01L21/76843 ,  C23C16/08 ,  H01L21/28061 ,  H01L21/28556 ,  H01L21/32051 ,  H01L21/76856 ,  H01L21/76876 ,  H01L21/76877

摘要： In situ nitridation of a thin layer of either silicon or tungsten provides an adhesive layer for bulk deposition of tungsten. Alternatively, a thin layer of silicon can be deposited directly on a dielectric, then reacted with WF6 to replace the silicon with tungsten, which provides a nucleation layer for bulk tungsten deposition.

摘要翻译： 硅或钨的薄层的原位氮化提供了用于钨的体积沉积的粘合剂层。 或者，可以将薄的硅层沉积在电介质上，然后与WF6反应以用钨代替硅，其提供用于体钨沉积的成核层。

公开(公告)号：US06559050B1

公开(公告)日：2003-05-06

申请号：US09691907

申请日：2000-10-19

申请人： William R. McKee ,  Jiong-Ping Lu ,  Ming-Jang Hwang ,  Dirk N. Anderson ,  Wei Lee

发明人： William R. McKee ,  Jiong-Ping Lu ,  Ming-Jang Hwang ,  Dirk N. Anderson ,  Wei Lee

IPC分类号： H01L2144

CPC分类号： H01L21/76843 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76867

摘要： A conducting plug/contact structure for use with integrated circuit includes a tungsten conducting plug formed in the via with a tungsten-silicon-nitride (WSiYNZ) region providing the interface between the tungsten conducting plug and the substrate (silicon) layer. The interface region is formed providing a nitrided surface layer over the exposed dielectric surfaces and the exposed substrate surface (i.e., exposed by a via in the dielectric layer) prior to the formation of tungsten/tungsten nitride layer filling the via. The structure is annealed forming a tungsten conducting plug with a tungsten-silicon-nitride interface between the conducting plug and the substrate. According to another embodiment, a tungsten nitride surface layer is formed over the nitrided surface layer prior to the formation of a tungsten layer to fill the via. According to another embodiment, a silicon surface layer is applied to the exposed surface of the dielectric layer and to the exposed surface of the substrate prior to formation of the nitrided surface layer. A layer of tungsten, tungsten/tungsten nitride, or tungsten nitride is formed to fill the via. After annealing, a tungsten conducting plug is formed with a tungsten-silicon-nitride interface region with the substrate.

摘要翻译： 与集成电路一起使用的导电插头/接触结构包括形成在通孔中的钨导电插塞，其中钨硅氮化物（WSiYNZ）区域提供钨导电插塞和衬底（硅）层之间的界面。 在形成填充通孔的钨/氮化钨层之前，形成界面区域，在暴露的电介质表面和暴露的衬底表面上（即，通过电介质层中的通孔暴露）提供氮化表面层。 该结构退火形成导电插塞和基板之间的钨 - 氮化硅界面的钨导电塞。 根据另一个实施例，在形成钨层以填充通孔之前，氮化表面层上形成氮化钨表面层。 根据另一实施例，在形成氮化表面层之前，将硅表面层施加到介电层的暴露表面和衬底的暴露表面。 形成一层钨，钨/氮化钨或氮化钨以填充通孔。 在退火之后，形成具有与基板的钨 - 氮化硅界面区域的钨导电塞。

公开(公告)号：US6120842A

公开(公告)日：2000-09-19

申请号：US954989

申请日：1997-10-21

申请人： Jiong-Ping Lu ,  Wei-Yung Hsu ,  Qi-Zhong Hong

发明人： Jiong-Ping Lu ,  Wei-Yung Hsu ,  Qi-Zhong Hong

IPC分类号： H01L21/02 ,  H01L21/285 ,  H01L21/302

CPC分类号： H01L28/75 ,  H01L21/28556 ,  H01L21/28568 ,  H01L28/55

摘要： A process for producing conformal and stable TiN+Al films, which provides flexibility in selecting the chemical composition and layering. In this new process, porous TiCN is first deposited, and then Al is incorporated by exposing the porous film to CVD aluminum conditions at low temperatures.

摘要翻译： 一种生产保形稳定的TiN + Al薄膜的方法，为选择化学成分和分层提供了灵活性。 在该新方法中，首先沉积多孔TiCN，然后通过在低温下将多孔膜暴露于CVD铝条件下而引入Al。

公开(公告)号：US6100188A

公开(公告)日：2000-08-08

申请号：US108474

申请日：1998-07-01

申请人： Jiong-Ping Lu ,  Ming Hwang ,  Dick N. Anderson ,  Duane E. Carter ,  Wei-Yung Hsu

发明人： Jiong-Ping Lu ,  Ming Hwang ,  Dick N. Anderson ,  Duane E. Carter ,  Wei-Yung Hsu

IPC分类号： H01L21/28 ,  H01L29/49 ,  H01L21/44

CPC分类号： H01L29/4941 ,  H01L21/28061

摘要： A metal-poly stack gate structure and associated method for forming a conductive barrier layer between W and poly in the metal-gate stack gate structure. The process includes the steps of depositing doped silicon on a substrate; forming nitride on the deposited silicon; depositing a metal on the nitride to form a metal/nitride/deposited silicon stack; and thermally treating the stack to transform the nitride into a conductive barrier layer between the metal and the deposited silicon. The thermal treatment transforms the nitride layer (SiN.sub.x or SiN.sub.x O.sub.y) into a conductive barrier (WSi.sub.x N.sub.y or WSi.sub.x N.sub.y O.sub.z) to form a W/barrier/poly stack gate structure. The barrier layer blocks reaction between W and Si, enhances sheet resistance, enhances adhesion between the W and the poly, and is stable at high temperatures.

摘要翻译： 一种用于在金属 - 栅极堆叠栅极结构中在W和多晶之间形成导电阻挡层的金属 - 多晶堆叠栅极结构和相关联的方法。 该方法包括在衬底上沉积掺杂硅的步骤; 在沉积的硅上形成氮化物; 在氮化物上沉积金属以形成金属/氮化物/沉积的硅堆叠; 并且对叠层进行热处理以将氮化物转变成金属和沉积的硅之间的导电阻挡层。 热处理将氮化物层（SiN x或SiN x O y）转换成导电屏障（WSixNy或WSixNyOz）以形成W /势垒/多晶堆叠栅极结构。 阻挡层阻止W和Si之间的反应，增强了薄层电阻，增强了W和聚硅之间的粘附性，并且在高温下是稳定的。

公开(公告)号：US6017818A

公开(公告)日：2000-01-25

申请号：US784657

申请日：1997-01-21

申请人： Jiong-Ping Lu

发明人： Jiong-Ping Lu

IPC分类号： H01L21/285 ,  H01L21/768 ,  H01L21/44 ,  H01L23/48

CPC分类号： H01L21/76856 ,  H01L21/28556 ,  H01L21/76843

摘要： A CVD process for Ti--Si--N or Ti--B--N films wherein a single feed gas (preferably TDMAT) serves as the source for titanium and nitrogen, and another feed gas is used as the source for silicon or boron. This avoids gas-phase particulate nucleation while providing good conformality. When the required thickness has been deposited, the silicon or boron feed gas continues to flow for some time after the titanium/nitrogen or titanium/boron source gas has been turned off. This results in a Ti--N film with a Si-rich or B-rich surface, which is conformal and has a low defect density. In a second embodiment, a single feed gas, such as TDMAT, is thermally decomposed to form a Ti--N layer. A post-deposition anneal is performed in a gas which supplies silicon or boron, incorporating these materials into the layer. The incorporation of silicon or boron into the layer minimizes the absorption of oxygen into the films, and therefore stabilizes the resulting films. The Si-rich or boron-rich surfaces are also helpful in wetting Al and enhancing adhesion to Cu, therefore are advantageous for advanced metallization application. Compared with the sputtering method, this invention offers a process for depositing films with much better step coverage and easier control of Si/Ti ratio. Compared with the TDEAT+NH.sub.3 +SiH.sub.4 method, this invention eliminates the gas phase reaction between Ti source and NH.sub.3.

摘要翻译： 用于Ti-Si-N或Ti-B-N膜的CVD工艺，其中单个进料气体（优选TDMAT）用作钛和氮的源，并且另一个进料气体用作硅或硼的源。 这避免了气相微粒成核同时提供良好的共形性。 当所需的厚度已经沉积时，在钛/氮或钛/硼源气体已被关闭之后，硅或硼原料气继续流动一段时间。 这导致具有富Si或富B表面的Ti-N膜，其是共形的并且具有低缺陷密度。 在第二实施例中，单个进料气体，例如TDMAT，被热分解以形成Ti-N层。 在提供硅或硼的气体中进行后沉积退火，将这些材料并入该层中。 将硅或硼引入该层使得氧进入薄膜的吸收最小化，从而稳定所得薄膜。 富Si或富含硼的表面也有助于润湿Al和增强对Cu的粘合性，因此有利于高级金属化应用。 与溅射方法相比，本发明提供了一种沉积膜的方法，其具有更好的步骤覆盖率和更容易控制Si / Ti比。 与TDEAT + NH3 + SiH4方法相比，本发明消除了Ti源和NH3之间的气相反应。

公开(公告)号：US6008540A

公开(公告)日：1999-12-28

申请号：US87458

申请日：1998-05-28

申请人： Jiong-Ping Lu ,  Changming Jin

发明人： Jiong-Ping Lu ,  Changming Jin

IPC分类号： H01L21/3105 ,  H01L21/314 ,  H01L21/316 ,  H01L21/762 ,  H01L21/768 ,  H01L23/29 ,  H01L23/522 ,  H01L23/532 ,  H01L23/48 ,  H01L23/58 ,  H01L47/00

CPC分类号： H01L21/76819 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/02337 ,  H01L21/02343 ,  H01L21/02359 ,  H01L21/02362 ,  H01L21/31695 ,  H01L21/76224 ,  H01L21/76801 ,  H01L21/7682 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76837 ,  H01L23/296 ,  H01L23/5222 ,  H01L23/5329 ,  H01L21/3105 ,  H01L2221/1047 ,  H01L2924/0002

摘要： A surface treatment for porous silica to enhance adhesion of overlying layers. Treatments include surface group substitution, pore collapse, and gap filling layer (520) which invades open surface pores (514) of xerogel (510).

公开(公告)号：US07732313B2

公开(公告)日：2010-06-08

申请号：US12348660

申请日：2009-01-05

申请人： Jiong-Ping Lu ,  Yaw S. Obeng ,  Ping Jiang ,  Joe G. Tran

发明人： Jiong-Ping Lu ,  Yaw S. Obeng ,  Ping Jiang ,  Joe G. Tran

IPC分类号： H01L21/44

CPC分类号： H01L21/31055 ,  H01L21/28097 ,  H01L21/32134 ,  H01L29/4975 ,  H01L29/6656 ,  H01L29/7833

摘要： A method for making a transistor 20 that includes using a transition metal nitride layer 200 and/or a SOG layer 220 to protect the source/drain regions 60 from silicidation during the silicidation of the gate electrode 90. The SOG layer 210 is planarized to expose the transition metal nitride layer 200 or the gate electrode 93 before the gate silicidation process. If a transition metal nitride layer 200 is used, then it is removed from the top of the gate electrode 93 before the full silicidation of the gate electrode 90.

摘要翻译： 一种制造晶体管20的方法，其包括使用过渡金属氮化物层200和/或SOG层220来保护源极/漏极区域60在栅电极90的硅化期间不被硅化。SOG层210被平坦化以暴露 在栅极硅化处理之前的过渡金属氮化物层200或栅电极93。 如果使用过渡金属氮化物层200，则在栅电极90完全硅化之前，从栅电极93的顶部去除它。