公开(公告)号：US07417302B2

公开(公告)日：2008-08-26

申请号：US11174864

申请日：2005-07-05

Applicant: Kyoung-Woo Lee ,  Hong-Jae Shin ,  Jeong-Hoon Ahn ,  Seung-Man Choi ,  Byung-Jun Oh ,  Yoon-Hae Kim

Inventor： Kyoung-Woo Lee ,  Hong-Jae Shin ,  Jeong-Hoon Ahn ,  Seung-Man Choi ,  Byung-Jun Oh ,  Yoon-Hae Kim

IPC: H01L29/00

CPC classification number: H01L23/5223 ,  H01L21/76808 ,  H01L21/76877 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a method of manufacturing a semiconductor device, a first insulation layer on the substrate is patterned to form a first opening having a first width. A lower electrode is formed along an inner contour of the first opening. A second insulation layer on the first insulation layer is patterned to form a second opening that has a second width greater than the first width and is connected to the first opening with a stepped portion. A dielectric layer is formed on the lower electrode in the first opening, a sidewall of the second opening and a first stepped portion between the first insulation layer and the second insulation layer, so that the electrode layer is covered with the dielectric layer. An upper electrode is formed on the dielectric layer. Accordingly, a leakage current between the lower and upper electrodes is suppressed.

Abstract translation: 在制造半导体器件的方法中，将衬底上的第一绝缘层图案化以形成具有第一宽度的第一开口。 沿着第一开口的内轮廓形成下电极。 第一绝缘层上的第二绝缘层被图案化以形成具有大于第一宽度的第二宽度的第二开口，并且连接到具有台阶部分的第一开口。 在第一开口的下电极，第二开口的侧壁和第一绝缘层与第二绝缘层之间的第一台阶部分上形成电介质层，使电极层被电介质层覆盖。 在电介质层上形成上电极。 因此，抑制了下电极和上电极之间的漏电流。

公开(公告)号：US07064059B2

公开(公告)日：2006-06-20

申请号：US10939930

申请日：2004-09-13

Applicant: Jae-Hak Kim ,  Young-Joon Moon ,  Kyoung-Woo Lee ,  Jeong-Wook Hwang

Inventor： Jae-Hak Kim ,  Young-Joon Moon ,  Kyoung-Woo Lee ,  Jeong-Wook Hwang

IPC: H01L21/4763 ,  H01L21/311 ,  H01L21/302 ,  H01L21/461

CPC classification number: H01L21/76808 ,  H01L21/31144

Abstract: There is provided a method of forming a dual damascene metal interconnection by employing a sacrificial metal oxide layer. The method includes preparing a semiconductor substrate. An interlayer insulating layer is formed on the semiconductor substrate, and a preliminary via hole is formed by patterning the interlayer insulating layer. A sacrificial via protecting layer is formed on the semiconductor substrate having the preliminary via hole to fill the preliminary via hole, and cover an upper surface of the interlayer insulating layer. A sacrificial metal oxide layer is formed on the sacrificial via protecting layer, the sacrificial metal oxide layer is patterned to form a sacrificial metal oxide pattern having an opening crossing over the preliminary via hole, and exposing the sacrificial via protecting layer. The sacrificial via protecting layer and the interlayer insulating layer are etched using the sacrificial metal oxide pattern as an etch mask to form a trench located inside the interlayer insulating layer.

Abstract translation: 提供了通过使用牺牲金属氧化物层形成双镶嵌金属互连的方法。 该方法包括制备半导体衬底。 在半导体基板上形成层间绝缘层，通过图案化层间绝缘层形成预备通孔。 在具有初步通孔的半导体衬底上形成牺牲通孔保护层以填充预通孔，并覆盖层间绝缘层的上表面。 在牺牲通路保护层上形成牺牲金属氧化物层，对牺牲金属氧化物层进行图案化以形成具有穿过预通孔的开口的牺牲金属氧化物图案，并且将牺牲通过保护层曝光。 使用牺牲金属氧化物图案作为蚀刻掩模蚀刻牺牲通过保护层和层间绝缘层，以形成位于层间绝缘层内部的沟槽。

公开(公告)号：US20060063376A1

公开(公告)日：2006-03-23

申请号：US11195404

申请日：2005-08-02

Applicant: Kyoung-woo Lee ,  Jae-yeol Maeng ,  Jae-hak Kim ,  Il-whan Oh ,  Hong-jae Shin

Inventor： Kyoung-woo Lee ,  Jae-yeol Maeng ,  Jae-hak Kim ,  Il-whan Oh ,  Hong-jae Shin

IPC: H01L21/4763 ,  H01L21/31

CPC classification number: H01L21/76808 ,  H01L21/02134 ,  H01L21/3124 ,  H01L21/76826

Abstract: Methods of fabricating dual damascene interconnections suitable for use in microelectronic devices and similar applications using a diffusion barrier layer to protect against base materials during processing are provided. The methods include the steps of: filling a via with a hydrogen silsesquioxane (HSQ)-based filler as expressed by the general chemical formula: (RSiO3/2)x(HSiO3/2)y, wherein x and y satisfy the relationships x+y=1 and 0

Abstract translation: 提供了适用于微电子器件的双镶嵌互连的方法和使用扩散阻挡层在加工期间防止基底材料的类似应用。 所述方法包括以下步骤：用以通式（RSiO 3/2/2）x（HSiO 3/2/2）表示的氢倍半硅氧烷（HSQ））填充通孔 y，其中x和y满足关系x + y = 1和0

公开(公告)号：US06936533B2

公开(公告)日：2005-08-30

申请号：US09994508

申请日：2001-11-27

Applicant: Jae-Hak Kim ,  Hong-Jae Shin ,  Soo-Geun Lee ,  Kyoung-Woo Lee

Inventor： Jae-Hak Kim ,  Hong-Jae Shin ,  Soo-Geun Lee ,  Kyoung-Woo Lee

IPC: H01L21/314 ,  H01L21/316 ,  H01L21/768 ,  H01L21/4763 ,  H01L21/31 ,  H01L23/58

CPC classification number: H01L21/76826 ,  H01L21/02126 ,  H01L21/02137 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/0234 ,  H01L21/02362 ,  H01L21/3144 ,  H01L21/31633 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76807 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating a semiconductor device having a low dielectric constant is disclosed. According to the method, a silicon oxycarbide layer is formed, treated with plasma, and patterned. The silicon oxycarbide layer is formed by a coating method or a CVD method such as a PECVD method. Treating the silicon oxycarbide layer with plasma is performed by supplying at least one gas selected from a group of He, H2, N2O, NH3, N2, O2 and Ar. It is desirable that plasma be applied at the silicon oxycarbide layer in a PECVD device by an in situ method after forming the silicon oxycarbide layer. In a case in which a capping layer is further stacked and patterned, it is desirable to treat with H2-plasma. Even in a case in which an interlayer insulation is formed of the silicon oxycarbide layer and a coating layer of an organic polymer group for a dual damascene process, it is desirable to perform the plasma treatment before forming the coating layer.

Abstract translation: 公开了一种制造具有低介电常数的半导体器件的方法。 根据该方法，形成碳氧化硅层，用等离子体处理并图案化。 碳硅氧化物层通过涂布法或CVD法如PECVD法形成。 用等离子体处理碳氧化硅层是通过供给至少一种选自He，H 2 H 2，N 2 O，NH 3， N 2，N 2，O 2和Ar。 希望在形成硅碳化硅层之后，通过原位法将等离子体施加在PECVD器件中的碳氧化硅层。 在封盖层进一步堆叠和图案化的情况下，希望用H 2 - 等离子体处理。 即使在由硅碳化硅层和双镶嵌工艺的有机聚合物基团的涂层形成层间绝缘的情况下，期望在形成涂层之前进行等离子体处理。

公开(公告)号：US06855629B2

公开(公告)日：2005-02-15

申请号：US10437529

申请日：2003-05-14

Applicant: Jae-Hak Kim ,  Soo-Geun Lee ,  Wan-Jae Park ,  Kyoung-Woo Lee

Inventor： Jae-Hak Kim ,  Soo-Geun Lee ,  Wan-Jae Park ,  Kyoung-Woo Lee

IPC: H01L21/28 ,  H01L21/768 ,  H01L21/4763

CPC classification number: H01L21/76808

Abstract: In a method for forming a dual damascene wiring pattern, an etch stop film and an interlayer dielectric film comprising an SiOC:H group material are formed on a substrate having an electrical connection layer formed thereon. An anti-reflection layer is formed on the interlayer dielectric film. A primary opening is formed by etching the anti-reflection layer and the interlayer dielectric film to expose a surface of the etch stop film. A sacrificial film is formed comprising a low dielectric constant material in the primary opening and on the anti-reflection layer. A trench photoresist pattern having a width larger than that of the primary opening is formed on the sacrificial film after plasma-processing the sacrificial film. The sacrificial film, the anti-reflection layer and the interlayer dielectric film are sequentially etched using the trench photoresist pattern as an etch mask so as to form a secondary opening of a trench shape, and the trench photoresist pattern is removed, said secondary opening extending from an upper portion of the primary opening. The sacrificial film remaining is removed, the exposed etch stop film and anti-reflection layer are removed, the primary and secondary openings are filled with metal so as to be electrically coupled with the electrical connection layer. In this manner, damage to the etch stop layer is mitigated or eliminated during processing.

Abstract translation: 在形成双镶嵌布线图案的方法中，在其上形成有电连接层的基板上形成蚀刻停止膜和包含SiOC:H基材料的层间电介质膜。 在层间电介质膜上形成防反射层。 通过蚀刻抗反射层和层间电介质膜形成初级开口以暴露蚀刻停止膜的表面。 在初级开口和抗反射层中形成包括低介电常数材料的牺牲膜。 在等离子体处理牺牲膜之后，在牺牲膜上形成具有大于初级开口的宽度的沟槽光致抗蚀剂图案。 使用沟槽光致抗蚀剂图案作为蚀刻掩模，依次蚀刻牺牲膜，抗反射层和层间电介质膜，以形成沟槽形状的次级开口，并移除沟槽光致抗蚀剂图案，所述次级开口延伸 从主开口的上部。 去除残留的牺牲膜，去除暴露的蚀刻停止膜和抗反射层，用金属填充初级和次级开口以与电连接层电耦合。 以这种方式，在处理期间减轻或消除对蚀刻停止层的损伤。

公开(公告)号：US20050029010A1

公开(公告)日：2005-02-10

申请号：US10891062

申请日：2004-07-15

Applicant: Jeong-hoon Ahn ,  Hyo-jong Lee ,  Kyung-tae Lee ,  Kyoung-woo Lee ,  Soo-geun Lee ,  Bong-seok Suh

Inventor： Jeong-hoon Ahn ,  Hyo-jong Lee ,  Kyung-tae Lee ,  Kyoung-woo Lee ,  Soo-geun Lee ,  Bong-seok Suh

IPC: H01L21/768 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/4763 ,  H01L23/52 ,  H05K1/11

CPC classification number: H01L21/76877 ,  H01L21/76847

Abstract: A metal interconnection structure includes a lower metal interconnection layer disposed in a first inter-layer dielectric layer. An inter-metal dielectric layer having a via contact hole that exposes a portion of surface of the lower metal layer pattern is disposed on the first inter-layer dielectric layer and the lower metal layer pattern. A second inter-layer dielectric layer having a trench that exposes the via contact hole is formed on the inter-metal dielectric layer. A barrier metal layer is formed on a vertical surface of the via contact and the exposed surface of the second lower metal interconnection layer pattern. A first upper metal interconnection layer pattern is disposed on the barrier metal layer, thereby filling the via contact hole and a portion of the trench. A void diffusion barrier layer is disposed on the first metal interconnection layer pattern and a second upper metal interconnection layer pattern is disposed on the void diffusion barrier layer to completely fill the trench.

Abstract translation: 金属互连结构包括设置在第一层间电介质层中的下金属互连层。 具有暴露下部金属层图案的一部分表面的通孔接触孔的金属间介电层设置在第一层间电介质层和下部金属层图案上。 在金属间电介质层上形成具有暴露通孔接触孔的沟槽的第二层间电介质层。 在通孔接触件的垂直表面和第二下部金属互连层图案的暴露表面上形成阻挡金属层。 第一上金属互连层图案设置在阻挡金属层上，从而填充通孔接触孔和沟槽的一部分。 空隙扩散阻挡层设置在第一金属互连层图案上，并且第二上金属互连层图案设置在空隙扩散阻挡层上以完全填充沟槽。

公开(公告)号：US06828229B2

公开(公告)日：2004-12-07

申请号：US10081661

申请日：2002-02-22

Applicant: Soo-geun Lee ,  Hong-jae Shin ,  Kyoung-woo Lee ,  Jae-hak Kim

Inventor： Soo-geun Lee ,  Hong-jae Shin ,  Kyoung-woo Lee ,  Jae-hak Kim

IPC: H01L214763

CPC classification number: H01L21/76808 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144

Abstract: A method of forming an interconnection line in a semiconductor device is provided. A first etching stopper is formed on a lower conductive layer which is formed on a semiconductor substrate. A first interlayer insulating layer is formed on the first etching stopper. A second etching stopper is formed on the first interlayer insulating layer. A second interlayer insulating layer is formed on the second etching stopper. The second interlayer insulating layer, the second etching stopper, and the first interlayer insulating layer are sequentially etched using the first etching stopper as an etching stopping point to form a via hole aligned with the lower conductive layer. A protective layer is formed to protect a portion of the first etching stopper exposed at the bottom of the via hole. A portion of the second interlayer insulating layer adjacent to the via hole is etched using the second etching stopper as an etching stopping point to form a trench connected to the via hole. The protective layer is removed. The portion of the first etching stopper positioned at the bottom of the via hole is removed. An upper conductive layer that fills the via hole and the trench and is electrically connected to the lower conductive layer is formed.

Abstract translation: 提供了一种在半导体器件中形成互连线的方法。 在形成在半导体衬底上的下导电层上形成第一蚀刻阻挡层。 在第一蚀刻停止件上形成第一层间绝缘层。 在第一层间绝缘层上形成第二蚀刻阻挡层。 在第二蚀刻停止件上形成第二层间绝缘层。 使用第一蚀刻停止器作为蚀刻停止点，依次蚀刻第二层间绝缘层，第二蚀刻停止层和第一层间绝缘层，以形成与下导电层对准的通孔。 形成保护层以保护暴露在通孔底部的第一蚀刻终止部分。 使用第二蚀刻停止器蚀刻与通孔相邻的第二层间绝缘层的一部分作为蚀刻停止点，以形成连接到通孔的沟槽。 保护层被去除。 位于通孔底部的第一蚀刻停止部分被去除。 形成填充通孔和沟槽并与下导电层电连接的上导电层。

公开(公告)号：US10229876B2

公开(公告)日：2019-03-12

申请号：US15073640

申请日：2016-03-17

Applicant: Jun-Jung Kim ,  Young-Bae Kim ,  Jong-Sam Kim ,  Jin-Hyeung Park ,  Jeong-Hoon Ahn ,  Hyeok-Sang Oh ,  Kyoung-Woo Lee ,  Hyo-Seon Lee ,  Suk-Hee Jang

Inventor： Jun-Jung Kim ,  Young-Bae Kim ,  Jong-Sam Kim ,  Jin-Hyeung Park ,  Jeong-Hoon Ahn ,  Hyeok-Sang Oh ,  Kyoung-Woo Lee ,  Hyo-Seon Lee ,  Suk-Hee Jang

IPC: H01L23/535 ,  H01L23/528 ,  H01L23/522 ,  H01L27/088 ,  H01L23/532 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/485

Abstract: A wiring structure includes a substrate, a lower insulation layer on the substrate, a lower wiring in the lower insulation layer, a first etch-stop layer covering the lower wiring and including a metallic dielectric material, a second etch-stop layer on the first etch-stop layer and the lower insulation layer, an insulating interlayer on the second etch-stop layer, and a conductive pattern extending through the insulating interlayer, the second etch-stop layer and the first etch-stop layer and electrically connected to the lower wiring.

公开(公告)号：US08298911B2

公开(公告)日：2012-10-30

申请号：US13080001

申请日：2011-04-05

Applicant: Kyoung-Woo Lee

Inventor： Kyoung-Woo Lee

IPC: H01L21/76

CPC classification number: H01L21/7682 ,  H01L21/76831 ,  H01L21/76835 ,  H01L21/76849 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a method of forming a wiring structure, a first insulation layer is formed on a substrate, the first insulation layer comprising a group of hydrocarbon (CαHβ) wherein α and β are integers. A second insulation layer is formed on the first insulation layer, the second insulation layer being avoid of the group of hydrocarbon. A first opening is formed through the first and the second insulation layers by etching the first and the second insulation layers. A damaged pattern and a first insulation layer pattern are formed by performing a surface treatment on a portion of the first insulation layer corresponding to an inner sidewall of the first opening. A sacrificial spacer is formed in the first opening on the damaged pattern and on the second insulation layer. A conductive pattern is formed in the first opening. The sacrificial spacer and the damaged pattern are removed to form a first air gap between the conductive pattern and the first insulation layer pattern, and to form a second air gap between the conductive pattern and the second insulation layer.

Abstract translation: 在形成布线结构的方法中，在基板上形成第一绝缘层，所述第一绝缘层包含一组烃（CαH＆bgr），其中α和bgr; 是整数。 在第一绝缘层上形成第二绝缘层，第二绝缘层避免了一组烃。 通过蚀刻第一绝缘层和第二绝缘层，通过第一和第二绝缘层形成第一开口。 通过对与第一开口的内侧壁对应的第一绝缘层的一部分进行表面处理，形成损伤图案和第一绝缘层图案。 在损伤图案上的第一开口和第二绝缘层上形成牺牲隔离物。 在第一开口中形成导电图案。 除去牺牲隔离物和损伤图案以在导电图案和第一绝缘层图案之间形成第一气隙，并在导电图案和第二绝缘层之间形成第二气隙。

公开(公告)号：US20100244255A1

公开(公告)日：2010-09-30

申请号：US12661866

申请日：2010-03-25

Applicant: Kyoung-Woo Lee

Inventor： Kyoung-Woo Lee

IPC: H01L23/532

CPC classification number: H01L23/5222 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76835 ,  H01L21/76849 ,  H01L23/53295 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A wiring structure includes a conductive pattern on a substrate, a first insulation layer pattern between adjacent conductive patterns and a second insulation layer pattern on the first insulation layer pattern. The first insulation layer pattern is separated from the conductive pattern by a first distance to provide a first air gap. The second insulation layer pattern is spaced apart from the conductive pattern by a second distance substantially smaller than the first distance to provide a second air gap. The wiring structure may have a reduced parasitic capacitance while simplifying processes for forming the wiring structure.

Abstract translation: 布线结构包括在基板上的导电图案，相邻导电图案之间的第一绝缘层图案和第一绝缘层图案上的第二绝缘层图案。 第一绝缘层图案与导电图案分离第一距离以提供第一气隙。 第二绝缘层图案与导电图案间隔开第二距离，该距离基本上小于第一距离以提供第二气隙。 布线结构可以具有减小的寄生电容，同时简化用于形成布线结构的工艺。