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    READOUT APPARATUS FOR CURRENT TYPE TOUCH PANEL
    51.
    发明申请
    READOUT APPARATUS FOR CURRENT TYPE TOUCH PANEL 审中-公开
    电流型触控面板的读出装置

    公开(公告)号：US20120139529A1

    公开(公告)日：2012-06-07

    申请号：US13370219

    申请日：2012-02-09

    Applicant: Kai-Lan Chuang ,  Guo-Ming Lee ,  Ying-Lieh Chen

    Inventor： Kai-Lan Chuang ,  Guo-Ming Lee ,  Ying-Lieh Chen

    IPC: G01R11/04

    CPC classification number: G06F3/0416

    Abstract: A readout apparatus for a current type touch panel is provided. The readout apparatus includes a current-to-voltage converter, a voltage gain unit and an analog-to-digital converter (ADC). The current-to-voltage converter converts a sensing current of the current type touch panel to a sensing voltage. The current-to-voltage converter includes a resistor and a current mirror. The resistor has a first end and a second end. The current mirror has a master current end and a slave current end. An input end of the voltage gain unit is coupled to an output end of the current-to-voltage converter for receiving the sensing voltage. An input end of the ADC is coupled to an output end of the voltage gain unit. An output end of the ADC generates a digital code.

    Abstract translation: 本发明提供一种用于电流型触摸面板的读出装置。 读出装置包括电流 - 电压转换器，电压增益单元和模 - 数转换器（ADC）。 电流 - 电压转换器将当前类型的触摸面板的感测电流转换为感测电压。 电流 - 电压转换器包括电阻和电流镜。 电阻器具有第一端和第二端。 电流镜具有主电流端和从电流端。 电压增益单元的输入端耦合到电流 - 电压转换器的输出端，用于接收感测电压。 ADC的输入端耦合到电压增益单元的输出端。 ADC的输出端产生数字代码。

    Manufacturing method of circuit structure
    53.
    发明授权
    Manufacturing method of circuit structure 有权
    电路结构的制造方法

    公开(公告)号：US08161638B2

    公开(公告)日：2012-04-24

    申请号：US12783806

    申请日：2010-05-20

    Applicant: Tzyy-Jang Tseng ,  Chang-Ming Lee ,  Wen-Fang Liu ,  Cheng-Po Yu

    Inventor： Tzyy-Jang Tseng ,  Chang-Ming Lee ,  Wen-Fang Liu ,  Cheng-Po Yu

    IPC: H01K3/10

    CPC classification number: H05K3/465 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/184 ,  H05K3/421 ,  H05K3/4661 ,  H05K2201/0166 ,  H05K2201/0195 ,  H05K2203/1152 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T156/1056

    Abstract: A manufacturing method of circuit structure is described as follows. Firstly, a composite dielectric layer, a circuit board and an insulating layer disposed therebetween are provided. The composite dielectric layer includes a non-platable dielectric layer and a platable dielectric layer between the non-platable dielectric layer and the insulating layer wherein the non-platable dielectric layer includes a chemical non-platable material and the platable dielectric layer includes a chemical platable material. Then, the composite dielectric layer, the circuit board and the insulating layer are compressed. Subsequently, a through hole passing through the composite dielectric layer and the insulating layer is formed and a conductive via connecting a circuit layer of the circuit board is formed therein. Then, a trench pattern passing through the non-platable dielectric layer is formed on the composite dielectric layer. Subsequently, a chemical plating process is performed to form a conductive pattern in the trench pattern.

    Abstract translation: 电路结构的制造方法如下所述。 首先，提供复合电介质层，电路基板和设置在它们之间的绝缘层。 复合电介质层包括不可镀介电层和介于非平板电介质层和绝缘层之间的可镀介电层，其中非可镀介电层包括化学不可镀材料，并且可镀介电层包括化学镀层 材料。 然后，复合介电层，电路板和绝缘层被压缩。 随后，形成穿过复合介电层和绝缘层的通孔，并且在其中形成连接电路板的电路层的导电通孔。 然后，在复合电介质层上形成通过非电介质层的沟槽图案。 随后，执行化学镀处理以在沟槽图案中形成导电图案。

    Automatic fall behind warning method and system
    54.
    发明授权
    Automatic fall behind warning method and system 有权
    自动落后于警告方法和系统

    公开(公告)号：US08130678B2

    公开(公告)日：2012-03-06

    申请号：US12405249

    申请日：2009-03-17

    Applicant: Kuen-Ming Lee ,  Jenn-Lien Chu ,  Yu-Shiang Sheng

    Inventor： Kuen-Ming Lee ,  Jenn-Lien Chu ,  Yu-Shiang Sheng

    IPC: H04L12/28 ,  H04M11/00 ,  H04W24/00

    CPC classification number: H04L67/26 ,  H04L41/0893 ,  H04L41/12 ,  H04L67/18 ,  H04W4/02 ,  H04W4/023 ,  H04W40/248

    Abstract: Disclosed relates to an automatic fall behind warning method and system applied in a group activity environment. Each individual in the group corresponds to a node and all of such nodes form an independent network. The method initializes an outside node table for the group and gets a link quality index table (LQI table) among the nodes on the network. A table specifying outside and inside nodes for the network topology is generated via an algorithm. Then the method checks if there is a node being disappearing from the outside nodes of the generated table. If not, it updates the outside node table and continues to get a newest LQI table. If so, the node falls behind is confirmed and a warning notice is automatically generated once the disappearing node is not an inside node is verified. Otherwise, the method returns to the step of updating the outside node table.

    Abstract translation: 本发明涉及在群体活动环境中应用的警告方法和系统的自动落后。 组中的每个人对应于节点，并且所有这些节点形成独立网络。 该方法初始化组的外部节点表，并在网络中的节点中获取链路质量索引表（LQI表）。 通过算法生成指定用于网络拓扑的外部和内部节点的表。 然后该方法检查是否有一个节点从生成的表的外部节点消失。 如果没有，则更新外部节点表，并继续获取最新的LQI表。 如果是，则确认落后的节点，一旦消失的节点不是内部节点被验证，则自动生成警告通知。 否则，该方法返回到更新外部节点表的步骤。

    METHOD FOR OPERATING SEMICONDUCTOR DEVICE
    56.
    发明申请
    METHOD FOR OPERATING SEMICONDUCTOR DEVICE 有权
    操作半导体器件的方法

    公开(公告)号：US20120038414A1

    公开(公告)日：2012-02-16

    申请号：US13282482

    申请日：2011-10-27

    Applicant: Sung-Nien Tang ,  Wei-Lun Hsu ,  Ching-Ming Lee ,  Te-Yuan Wu

    Inventor： Sung-Nien Tang ,  Wei-Lun Hsu ,  Ching-Ming Lee ,  Te-Yuan Wu

    IPC: G05F3/02

    CPC classification number: H01L27/085 ,  H01L29/7817 ,  H03F3/195

    Abstract: A method for operating a semiconductor device including a lateral double diffused metal oxide semiconductor (LDMOS) with a first source, a common drain and a first gate, a junction field effect transistor (JFET) with a second source, the common drain and a second gate wherein the second source is electrically connected to the first gate and an inner circuit electrically connected to the first source is provided. The first source provides the inner circuit with an inner current to generate an inner voltage by means of the lateral double diffused metal oxide semiconductor, and the lateral double diffused metal oxide semiconductor turns off when the inner voltage is elevated substantially as high as the first gate voltage.

    Abstract translation: 一种用于操作包括具有第一源极，公共漏极和第一栅极的横向双扩散金属氧化物半导体（LDMOS）的半导体器件的方法，具有第二源极的结型场效应晶体管（JFET），所述公共漏极和第二源极 栅极，其中第二源极电连接到第一栅极，并且提供与第一源电连接的内部电路。 第一源为内部电路提供内部电流，以通过横向双扩散金属氧化物半导体产生内部电压，并且当内部电压升高到与第一栅极高相同时，横向双扩散金属氧化物半导体截止 电压。

    Semiconductor device and method for operating the same
    58.
    发明授权
    Semiconductor device and method for operating the same 有权
    半导体装置及其操作方法

    公开(公告)号：US08072011B2

    公开(公告)日：2011-12-06

    申请号：US12573884

    申请日：2009-10-06

    Applicant: Sung-Nien Tang ,  Wei-Lun Hsu ,  Ching-Ming Lee ,  Te-Yuan Wu

    Inventor： Sung-Nien Tang ,  Wei-Lun Hsu ,  Ching-Ming Lee ,  Te-Yuan Wu

    IPC: H01L29/80 ,  H01L31/112

    CPC classification number: H01L27/085 ,  H01L29/7817 ,  H03F3/195

    Abstract: A semiconductor device includes a lateral double diffused metal oxide semiconductor (LDMOS) , a junction field effect transistor (JFET) and an inner circuit. The lateral double diffused metal oxide semiconductor includes a first source, a common drain and a first gate. The junction field effect transistor includes a second source, the common drain and a second gate. The second source is electrically connected to the first gate. The inner circuit is electrically connected to the first source.

    Abstract translation: 半导体器件包括横向双扩散金属氧化物半导体（LDMOS），结型场效应晶体管（JFET）和内部电路。 横向双扩散金属氧化物半导体包括第一源极，公共漏极和第一栅极。 结型场效应晶体管包括第二源极，公共漏极和第二栅极。 第二源电连接到第一栅极。 内部电路电连接到第一源。

    MEMORY SYSTEM CAPABLE OF ENHANCING WRITING PROTECTION AND RELATED METHOD
    59.
    发明申请
    MEMORY SYSTEM CAPABLE OF ENHANCING WRITING PROTECTION AND RELATED METHOD 有权
    能够加强书面保护的记忆体系和相关方法

    公开(公告)号：US20110289259A1

    公开(公告)日：2011-11-24

    申请号：US12900489

    申请日：2010-10-08

    Applicant: Hsu-Ming Lee

    Inventor： Hsu-Ming Lee

    IPC: G06F12/14 ,  G06F12/00

    CPC classification number: G11C16/22 ,  G06F12/1433 ,  G06F2212/2022

    Abstract: A memory system is disclosed. The memory system includes a memory device, a first control unit, and a second control unit. The memory device is utilized for storing data. The first control unit is coupled to the memory device for prohibiting a data writing process performed on the memory device during a writing protection period. The second control unit is coupled to the memory device for allowing the data writing process to be performed in the memory device according to a writing period after the writing protection period, wherein the writing period is related to the data writing process.

    Abstract translation: 公开了一种存储系统。 存储器系统包括存储器件，第一控制单元和第二控制单元。 存储器件用于存储数据。 第一控制单元耦合到存储器件，用于在写保护期间禁止对存储器件执行的数据写入处理。 第二控制单元耦合到存储器件，用于根据写保护周期之后的写入周期在存储器件中执行数据写入处理，其中写入周期与数据写入处理相关。

    NONVOLATILE MEMORY DEVICE
    60.
    发明申请
    NONVOLATILE MEMORY DEVICE 有权
    非易失性存储器件

    公开(公告)号：US20110280058A1

    公开(公告)日：2011-11-17

    申请号：US12778533

    申请日：2010-05-12

    Applicant: Yi-Chou Chen ,  Wei-Chih Chien ,  Feng-Ming Lee

    Inventor： Yi-Chou Chen ,  Wei-Chih Chien ,  Feng-Ming Lee

    IPC: G11C11/00 ,  G11C7/00

    CPC classification number: G11C13/0007 ,  G11C11/5685 ,  G11C13/0011 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/0076 ,  G11C2213/76 ,  G11C2213/79

    Abstract: A memory device comprises an array of memory cells each capable of storing multiple bits of data. Each memory cell includes a programmable transistor in series with a resistance switching device. The transistor is switchable between a plurality of different threshold voltages associated with respective memory states. The resistance switching device is configured to be switchable between a plurality of different resistances associated with respective memory states.

    Abstract translation: 存储器件包括每个能够存储多个数据位的存储器单元的阵列。 每个存储单元包括与电阻切换装置串联的可编程晶体管。 晶体管可在与各个存储器状态相关联的多个不同阈值电压之间切换。 电阻切换装置被配置为可在与各个存储器状态相关联的多个不同电阻之间切换。

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