公开(公告)号：US20240206169A1

公开(公告)日：2024-06-20

申请号：US18351992

申请日：2023-07-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masaaki HIGASHITANI ,  Peter RABKIN ,  Hiroyuki KINOSHITA

IPC: H10B43/27 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H10B43/30

CPC classification number: H10B43/27 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H10B43/30

Abstract: A semiconductor structure includes a vertical stack of repetition units, where each instance of the repetition unit extends along a first horizontal direction and includes a first electrically conductive strip, a first memory film located over the first electrically conductive strip, discrete semiconductor channels that are laterally spaced apart from each other along the first horizontal direction and located above the first memory film, a second memory film located above the discrete semiconductor channels, a second electrically conductive strip located above the second memory film, and an insulating strip located above the first electrically conductive strip. Source/drain openings are arranged along the first horizontal direction, interlaced with the discrete semiconductor channels, and vertically extending through the vertical stack of repetition units, and source/drain pillar structures are located in respective source/drain openings, and vertically extending through the vertical stack of repetition units.

公开(公告)号：US20240203512A1

公开(公告)日：2024-06-20

申请号：US18355343

申请日：2023-07-19

Applicant: SanDisk Technologies LLC

Inventor： Longju Liu ,  Sarath Puthenthermadam ,  Jiahui Yuan

IPC: G11C16/34 ,  G11C16/10

CPC classification number: G11C16/3459 ,  G11C16/10

Abstract: An apparatus is provided that includes a control circuit coupled to a plurality of non-volatile memory cells. The control circuit is configured to perform a program-verify iteration on a first set of the non-volatile memory cells in a plurality of program loops, determine that the first set of the non-volatile memory cells passes verification to a particular programmed state in a first number of program loops, determine a first voltage based on the first number of program loops, add an adaptive voltage offset to the first voltage to obtain a second voltage, and program a second set of the non-volatile memory cells in a plurality of program loops using the second voltage. The adaptive voltage offset varies as a function of temperature.

公开(公告)号：US20240201882A1

公开(公告)日：2024-06-20

申请号：US18220707

申请日：2023-07-11

Applicant: SanDisk Technologies LLC

Inventor： Jiacen Guo ,  Xiang Yang

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0604 ,  G06F3/0679

Abstract: The present disclosure is related to a programming technique for a memory device that includes a plurality of memory cells arranged in a plurality of word lines. An operating temperature of the memory device is determined. A spike pre-charge voltage is selected based on the operating temperature of the memory device. A first word line and a second word line are programmed in a first programming pass of a multi-pass programming operation. After the first programming pass is completed on the first and second word lines, the first word line is further programmed in a second programming pass that includes a plurality of program loops with pre-charge operations. The spike pre-charge voltage is applied to the second word line during each pre-charge operation.

公开(公告)号：US12014785B2

公开(公告)日：2024-06-18

申请号：US17511988

申请日：2021-10-27

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang

IPC: G11C16/04 ,  G11C16/34

CPC classification number: G11C16/3427 ,  G11C16/0483

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and arranged in strings. Each of the strings has a drain-side select gate transistor on a drain-side connected to one of a plurality of bit lines. A control means is coupled to the word lines and the plurality of bit lines and the drain-side select gate transistors. The control means determines a unique select gate voltage for each of a plurality of groupings of the memory cells that is individually adapted for each of the plurality of groupings. The control means then applies the unique select gate voltage to the drain-side select gate transistor of selected ones of the strings of each of the plurality of groupings of the memory cells to turn on the drain-side select gate transistor of the selected ones of the strings during a memory operation.

公开(公告)号：US20240196611A1

公开(公告)日：2024-06-13

申请号：US18351235

申请日：2023-07-12

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Keita YAMAMOTO

IPC: H10B43/27 ,  G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

CPC classification number: H10B43/27 ,  G11C16/0483 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a memory film, a vertical semiconductor channel, a dielectric core laterally surrounded by the vertical semiconductor channel, and a drain region overlying the dielectric core and the vertical semiconductor channel. The drain region includes an end cap portion and a hollow tubular portion vertically protruding downward from the end cap portion and laterally surrounding a top tip portion of the dielectric core.

公开(公告)号：US20240194277A1

公开(公告)日：2024-06-13

申请号：US18360306

申请日：2023-07-27

Applicant: SanDisk Technologies LLC

Inventor： Jiacen Guo ,  Xiang Yang ,  Yi Song ,  Jiahui Yuan

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/26

CPC classification number: G11C16/3459 ,  G11C16/08 ,  G11C16/26

Abstract: Technology is disclosed herein for a memory system that includes control circuits that are configured to connect to a three-dimensional memory structure. The memory structure includes NAND strings arranged in a plurality of rows, a plurality of bit lines connected to the NAND strings and a plurality of word lines, each word line coupled to the plurality of rows of NAND strings. The control circuits are configured to, in a program-verify operation, sense memory cells of a first row of NAND strings coupled to the selected word line for a first sense time and sense memory cells of a second row of NAND strings coupled to the selected word line for a second sense time while applying a program-verify voltage to the selected word line.

公开(公告)号：US20240194262A1

公开(公告)日：2024-06-13

申请号：US18354325

申请日：2023-07-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takayuki MAEKURA ,  Takaaki IWAI ,  Hiroyuki OGAWA

IPC: G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: G11C16/0483 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A three-dimensional memory device includes alternating stacks of insulating strips and electrically conductive strips, backside trenches located between neighboring pairs of alternating stacks, memory openings vertically extending through the alternating stacks, and memory opening fill structures located within the memory openings. In some embodiments, dielectric etch stop structures may be located within or outside the backside trenches such that each of the dielectric etch stop structures includes a respective pair of dielectric sidewalls that are located within a pair of lengthwise sidewalls of the respective one of the backside trenches. In some other embodiments, a dielectric isolation structure can laterally contact each of the insulating strips within the alternating stacks. Laterally insulated contact via structures can be provided to provide electrical contact to a respective one of the electrically conductive strips.

公开(公告)号：US12010841B2

公开(公告)日：2024-06-11

申请号：US17136471

申请日：2020-12-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Monica Titus ,  Senaka Kanakamedala ,  Rahul Sharangpani ,  Raghuveer S. Makala ,  Yao-Sheng Lee

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

Abstract: An alternating stack of first material layers and second material layers is formed over a substrate. A hard mask layer is formed over the alternating stack. Optionally, an additional hard mask layer can be formed over the hard mask layer. A photoresist layer is applied and patterned, and cavities are formed in the hard mask layer by performing a first anisotropic etch process that transfers a pattern of the openings in the photoresist layer through the hard mask layer. Via openings are formed through an upper portion of the alternating stack by performing a second anisotropic etch process. A cladding liner can be optionally formed on sidewalls of the cavities in the hard mask layer. The via openings can be vertically extend through all layers within the alternating stack by performing a third anisotropic etch process.

公开(公告)号：US12010835B2

公开(公告)日：2024-06-11

申请号：US17241321

申请日：2021-04-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhixin Cui ,  Satoshi Shimizu

IPC: H10B41/27 ,  G11C8/14 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B41/27 ,  G11C8/14 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory opening fill structures vertically extending through the alternating stack in a memory array region, and an electrically conductive spacer extending vertically and electrically connecting a first drain-select-level electrically conductive layer to a second drain-select-level electrically conductive layer.

公开(公告)号：US12009269B2

公开(公告)日：2024-06-11

申请号：US17725695

申请日：2022-04-21

Applicant: SanDisk Technologies LLC

Inventor： Cheng-Chung Chu ,  Masaaki Higashitani ,  Yusuke Ikawa ,  Seyyed Ehsan Esfahani Rashidi ,  Kei Samura ,  Tsuyoshi Sendoda ,  Yanli Zhang

IPC: H01L21/66 ,  H01L27/11578 ,  H10B43/20 ,  H10B43/10

CPC classification number: H01L22/14 ,  H01L22/12 ,  H01L22/26 ,  H10B43/20 ,  H10B43/10

Abstract: To provide more test data during the manufacture of non-volatile memories and other integrated circuits, machine learning is used to generate virtual test values. Virtual test results are interpolated for one set of tests for devices on which the test is not performed based on correlations with other sets of tests. In one example, machine learning determines a correlation study between bad block values determined at die sort and photo-limited yield (PLY) values determined inline during processing. The correlation can be applied to interpolate virtual inline PLY data for all of the memory dies, allowing for more rapid feedback on the processing parameters for manufacturing the memory dies and making the manufacturing process more efficient and accurate. In another set of embodiments, the machine learning is used to extrapolate limited metrology (e.g., critical dimension) test data to all of the memory die through interpolated virtual metrology data values.