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73 条记录 (耗时 0.019 秒)

    Lockstep processing systems and methods
    51.
    发明授权
    Lockstep processing systems and methods 有权

    公开(公告)号：US10725873B2

    公开(公告)日：2020-07-28

    申请号：US15995469

    申请日：2018-06-01

    申请人： Arm Limited

    发明人： Milosch Meriac ,  Shidhartha Das

    IPC分类号： G06F11/00 ,  G06F11/16 ,  G06F1/12

    摘要： The present techniques generally relate to a method of monitoring for a fault event in a lockstep processing system having a plurality of cores configured to operate in lockstep, the method having: power gating, for a period of time, a subset of cores of the plurality of cores from a first power source and providing power to the subset of cores from a second power source for the period of time; processing, at each of the cores of the plurality of cores, one or more instructions; providing an output from each core of the plurality of cores to error detection circuitry to monitor for the fault event, the output from each core based on or in response to processing the one or more instructions during the period of time.

    Observer Based Voltage Regulation Circuitry
    58.
    发明公开
    Observer Based Voltage Regulation Circuitry 审中-公开

    公开(公告)号：US20230291311A1

    公开(公告)日：2023-09-14

    申请号：US17690343

    申请日：2022-03-09

    申请人： Arm Limited

    发明人： Benoit Labbe ,  Shidhartha Das ,  Chi-Hsiang Huang

    IPC分类号： H02M3/157 ,  H02M3/158

    CPC分类号： H02M3/157 ,  H02M3/158

    摘要： Various implementations described herein are related to a device having a power stage that provides an output signal and a first feedback signal based on an input signal and a control signal. The device may have a digital stage with digital circuitry that provides a second feedback signal based on operational activity of the digital circuitry using the output signal. The device may have a control stage that provides the control signal based on the input signal, the first feedback signal and the second feedback signal.

    Clock phase-shifting techniques in physical layout design
    59.
    发明授权
    Clock phase-shifting techniques in physical layout design 有权

    公开(公告)号：US11444625B2

    公开(公告)日：2022-09-13

    申请号：US17103585

    申请日：2020-11-24

    申请人： Arm Limited

    发明人： Benoit Labbe ,  Shidhartha Das ,  Thanusree Achuthan

    IPC分类号： G06F1/00 ,  H03L7/081 ,  G06F1/324 ,  G06F1/10 ,  H03L7/085

    摘要： Various implementations described herein are related to a device. The device may include first circuitry that receives a clock signal and provides one or more phase-shifted pulse signals based on the clock signal. The device may include second circuitry that receives an input voltage, receives the clock signal, and provides an internal control signal based on the input voltage and the clock signal. The device may include third circuitry that receives the internal control signal, receives the one or more phase-shifted pulse signals, and provides an output clock signal based on the internal control signal and the one or more phase-shifted pulse signals.

    System-in-package architecture with wireless bus interconnect
    60.
    发明授权
    System-in-package architecture with wireless bus interconnect 有权

    公开(公告)号：US11366779B2

    公开(公告)日：2022-06-21

    申请号：US16685090

    申请日：2019-11-15

    申请人： Arm Limited ,  ECS Partners Limited

    发明人： Benjamin James Fletcher ,  James Edward Myers ,  Shidhartha Das ,  Terrence Sui Tung Mak

    IPC分类号： G06F13/40 ,  H04L12/40

    摘要： A chip-carrier package includes a data processing system having one or more slave dies, a master die and a system bus. Each slave die includes a slave device and a slave-side wireless bus interface (WBI) coupled to the slave device. The master die includes a master device, one or more bus-side WBIs coupled to the master device. Each bus-side WBI is configured to be wirelessly coupled to at least one slave-side WBI of the one or more slave dies and a system bus. The system bus includes the one or more bus-side WBIs and the slave-side WBIs of the one or more slave-side dies. The system bus is configured to exchange information between the master device and the slave devices of the one or more slave dies.