公开(公告)号：US20170373955A1

公开(公告)日：2017-12-28

申请号：US15192764

申请日：2016-06-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Brian J. Kocoloski ,  Leonardo Piga ,  Wei Huang ,  Indrani Paul

IPC: H04L12/26

CPC classification number: G06F11/30 ,  G06F9/4893 ,  G06F2209/5019 ,  Y02D10/24

Abstract: Systems, apparatuses, and methods for achieving balanced execution in a multi-node cluster through runtime detection of performance variation are described. During a training phase, performance counters and an amount of time spent waiting for synchronization is monitored for a plurality of tasks for each node of the multi-node cluster. These values are utilized to generate a model which correlates the values of the performance counters to the amount of time spent waiting for synchronization. Once the model is built, the values of the performance counters are monitored for a period of time at the start of each task, and these values are input into the model. The model generates a prediction of whether a given node is on the critical path. If the given node is predicted to be on the critical path, the power allocation of the given node is increased.

公开(公告)号：US09851777B2

公开(公告)日：2017-12-26

申请号：US14146591

申请日：2014-01-02

Applicant: Advanced Micro Devices, Inc.

Inventor： Manish Arora ,  Indrani Paul ,  Yasuko Eckert ,  Nuwan S. Jayasena ,  Srilatha Manne ,  Madhu Saravana Sibi Govindan ,  William L. Bircher

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/3225 ,  Y02D10/171 ,  Y02D50/20

Abstract: Power gating decisions can be made based on measures of cache dirtiness. Analyzer logic can selectively power gate a component of a processor system based on a cache dirtiness of one or more caches associated with the component. The analyzer logic may power gate the component when the cache dirtiness exceeds a threshold and may maintains the component in an idle state when the cache dirtiness does not exceed the threshold. Idle time prediction logic may be used to predict a duration of an idle time of the component. The analyzer logic may then selectively power gates the component based on the cache dirtiness and the predicted idle time.

公开(公告)号：US20170357509A1

公开(公告)日：2017-12-14

申请号：US15181837

申请日：2016-06-14

Applicant: Advanced Micro Devices, Inc.

Inventor： Akanksha Jain ,  Wei Huang ,  Indrani Paul

IPC: G06F9/30 ,  G06F1/32

CPC classification number: G06F9/30181 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3296 ,  G06F11/30

Abstract: A system-on-a-chip includes a plurality of instruction processors and a hardware block such as a system management unit. The hardware block accesses values of performance counters associated with the plurality of instruction processors and modifies one or more operating points of one or more of the plurality of instruction processors based on comparisons of the instruction arrival rates and the instruction service rates to achieve optimized system metrics.

公开(公告)号：US09658663B2

公开(公告)日：2017-05-23

申请号：US14862044

申请日：2015-09-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Wei Huang ,  Manish Arora ,  Yasuko Eckert ,  Indrani Paul

IPC: G06F1/28 ,  G06F1/30 ,  G06F1/20 ,  G06T1/20 ,  G06F1/32 ,  G06F11/30

CPC classification number: G06F1/206 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/3296 ,  G06F11/3024 ,  G06F11/3058

Abstract: A three-dimensional (3-D) processor stack includes a plurality of processor cores implemented in a plurality of layers. A controller is to selectively throttle one or more of a plurality of processor cores in response to detecting a thermal event. The controller selectively throttles the one or more of the plurality of processor cores based on values of thermal couplings between the plurality of layers and based on measures of criticality of threads executing on the plurality of processor cores.

公开(公告)号：US20160018870A1

公开(公告)日：2016-01-21

申请号：US14333976

申请日：2014-07-17

Applicant: Advanced Micro Devices, Inc.

Inventor： Manish Arora ,  Vignesh Trichy Ravi ,  Indrani Paul

IPC: G06F1/32

CPC classification number: G06F1/3212 ,  G06F1/263 ,  G06F1/3231 ,  G06F1/3296 ,  Y02D10/172 ,  Y02D10/173 ,  Y02D10/174

Abstract: An apparatus and methods for controlling energy consumption of an electronic device determine an availability of an energy source to provide energy to the electronic device. The apparatus and methods control, by power management control logic of the electronic device, energy consumption of the electronic device in response to determining the availability of the energy source.

Abstract translation: 用于控制电子设备的能量消耗的装置和方法确定能量源的可用性以向电子设备提供能量。 该装置和方法通过电子设备的电源管理控制逻辑来控制电子设备响应于确定能量源的可用性的能量消耗。

公开(公告)号：US20150304177A1

公开(公告)日：2015-10-22

申请号：US14255137

申请日：2014-04-17

Applicant: Advanced Micro Devices, Inc.

Inventor： Joseph L. Greathouse ,  Indrani Paul

IPC: H04L12/26 ,  H04L12/24

CPC classification number: H04L43/04 ,  H04L41/5009 ,  H04L41/5096 ,  H04L43/08

Abstract: Application performance data that indicates a level of service provided in executing one or more applications is determined in software running on one or more processor cores in a computing system that executes the one or more applications. The application performance data is provided to a controller in the computing system that is distinct from the one or more processor cores.

Abstract translation: 指示在执行一个或多个应用程序中提供的服务级别的应用程序性能数据在运行在执行一个或多个应用程序的计算系统中的一个或多个处理器核心上的软件中确定。 将应用性能数据提供给不同于一个或多个处理器核心的计算系统中的控制器。

公开(公告)号：US20150067357A1

公开(公告)日：2015-03-05

申请号：US14015578

申请日：2013-08-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Manish Arora ,  Nuwan S. Jayasena ,  Indrani Paul ,  Michael J. Schulte

IPC: G06F1/26

CPC classification number: G06F1/3206 ,  G06F1/3234 ,  G06F1/3237 ,  G06F1/3246 ,  G06F1/3287 ,  Y02D10/128 ,  Y02D10/171 ,  Y02D50/20

Abstract: The present application describes embodiments of methods for tournament prediction of power gating in processing devices. Some embodiments of the method include selecting one of a plurality of predictions of a duration of a time to a power state transition of a component in a processing device. The plurality of predictions are generated using a corresponding plurality of prediction algorithms. Some embodiments of the method also include deciding whether to transition the component from a first power state to a second power state based on the selected prediction.

Abstract translation: 本申请描述了处理设备中电源门控的比赛预测方法的实施例。 该方法的一些实施例包括选择一个时间持续时间的多个预测中的一个到处理设备中的组件的功率状态转换。 使用相应的多个预测算法生成多个预测。 该方法的一些实施例还包括基于所选择的预测来决定是否将分量从第一功率状态转换到第二功率状态。

公开(公告)号：US20140143565A1

公开(公告)日：2014-05-22

申请号：US14059384

申请日：2013-10-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Indrani Paul ,  Manish Arora ,  Srilatha Manne ,  William L. Bircher

IPC: G06F1/32

CPC classification number: G06F1/3206 ,  G06F1/206

Abstract: The described embodiments include a computing device with a first entity and a second entity. In the computing device, a management controller dynamically sets a power-state limit for the first entity based on a performance coupling and a thermal coupling between the first entity and the second entity.

Abstract translation: 所描述的实施例包括具有第一实体和第二实体的计算设备。 在计算设备中，管理控制器基于第一实体和第二实体之间的性能耦合和热耦合来动态地设置第一实体的功率状态极限。

公开(公告)号：US12271244B2

公开(公告)日：2025-04-08

申请号：US17390429

申请日：2021-07-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Benjamin Tsien ,  Indrani Paul ,  Alexander J. Branover ,  Thomas J. Gibney ,  Mihir Shaileshbhai Doctor ,  John P. Petry ,  Stephen V. Kosonocky ,  Christopher T. Weaver

IPC: G06F9/24 ,  G06F1/3203 ,  G06F9/4401

Abstract: Systems, methods, and devices for integrated circuit power management. A mode of a power management state is entered, from the power management state, in response to an entry condition of the mode. A device that is otherwise powered off in the power management state is powered on in the mode of the power management state. In some implementations, the device includes a communications path between a second device and a third device. In some implementations, the device is in a power domain that is powered off in the power management state. In some implementations, the power domain is powered off in the mode. In some implementations, the device is powered on in the mode via a power rail that is specific to the mode. In some implementations, the entry condition of the mode includes an amount of data stored for display in a display buffer falling below a threshold amount.

公开(公告)号：US12235708B2

公开(公告)日：2025-02-25

申请号：US17483702

申请日：2021-09-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Benjamin Tsien ,  Alexander J. Branover ,  Indrani Paul ,  Christopher T. Weaver ,  Thomas J. Gibney ,  Stephen V. Kosonocky ,  John P. Petry ,  Mihir Shaileshbhai Doctor

IPC: G06F1/32 ,  G06F1/3234

Abstract: Devices and methods for cache prefetching are provided. A device is provided which comprises a quality of service (QOS) component having first assigned registers used to store data to execute a program, a plurality of non-QOS components having second assigned registers used to store data to execute the program and a power management controller, in communication with the QOS component and the non-QOS components. The power management controller is configured to issue fences for the non-QOS components when it is determined that one or more of the non-QOS components are idle, issue a fence for the QOS component when the fences for the non-QOS components are completed and enter a reduced power state when the fences for the non-QOS components and the fence for the QOS component are completed.