公开(公告)号：US06472705B1

公开(公告)日：2002-10-29

申请号：US09195083

申请日：1998-11-18

Applicant: Donald Stimson Bethune ,  Sandip Tiwari

Inventor： Donald Stimson Bethune ,  Sandip Tiwari

IPC: H01L3524

CPC classification number: G11C13/025 ,  B82Y10/00 ,  G11C13/0014 ,  G11C23/00 ,  G11C2213/17 ,  H01L27/283 ,  H01L51/0046 ,  H01L51/0541 ,  H01L51/0545 ,  Y10S977/936 ,  Y10S977/937 ,  Y10S977/943

Abstract: The present invention is directed to a microelectric device and especially a Field effect transistor comprising a source, drain, channel, an insulating layer overlying said channel containing at least one closed cage molecule, said closed cage molecule being capable of exhibiting a Coulomb blockade effect upon application of a voltage between said source and drain. Two different microelectronic devices are described containing the closed cage molecule, a logic cell and a memory cell.

Abstract translation: 本发明涉及一种微电子器件，特别是一种场效应晶体管，其包括源极，漏极，沟道，覆盖所述沟道的绝缘层，所述绝缘层包含至少一个闭合笼状分子，所述封闭笼分子能够表现出库仑阻塞效应 在所述源极和漏极之间施加电压。 描述了包含封闭笼分子，逻辑单元和存储单元的两种不同的微电子器件。

公开(公告)号：US6137128A

公开(公告)日：2000-10-24

申请号：US94383

申请日：1998-06-09

Applicant: Steven John Holmes ,  Howard Leo Kalter ,  Sandip Tiwari ,  Jeffrey John Welser

Inventor： Steven John Holmes ,  Howard Leo Kalter ,  Sandip Tiwari ,  Jeffrey John Welser

IPC: H01L21/8242 ,  H01L27/108 ,  H01L29/94 ,  H01L29/76 ,  H01L31/119

CPC classification number: H01L27/10864 ,  H01L29/945 ,  H01L27/10823 ,  H01L27/1087

Abstract: A densely packed array of vertical semiconductor devices, having pillars, deep trench capacitors, vertical transistors, and methods of making thereof are disclosed. The pillars act as transistor channels, and may be formed utilizing the application of hybrid resist over a block of semiconductor material. Drain doped regions are formed on the top of each pillar. The source doped regions and the plate doped regions are self-aligned and are created by diffusion in the trenches surrounding the pillars. The array has columns of bitlines and rows of wordlines. The capacitors are formed by isolating n.sup.+ polysilicon in trenches separating said pillars. The array is suitable for GBit DRAM applications because the deep trench capacitors do not increase array area. The array may have an open bitline architecture, where the plate region is common to all the storage nodes or a folded architecture with two wordlines that pass through each cell having stacked transistors, where one wordline is active and the other is passing for each cell.

Abstract translation: 公开了一种密集堆叠的垂直半导体器件阵列，具有支柱，深沟槽电容器，垂直晶体管及其制造方法。 支柱用作晶体管通道，并且可以利用在半导体材料块上施加混合抗蚀剂来形成。 在每个支柱的顶部形成漏极掺杂区域。 源掺杂区域和板掺杂区域是自对准的，并且通过在柱子周围的沟槽中的扩散而产生。 该阵列具有位线和字线行。 通过在分离所述柱的沟槽中隔离n +多晶硅来形成电容器。 该阵列适用于GBit DRAM应用，因为深沟槽电容器不增加阵列面积。 阵列可以具有开放的位线架构，其中板区域对于所有存储节点是公共的，或者具有两个字线的折叠结构，其中两个字线通过具有堆叠晶体管的每个单元，其中一个字线是活动的，而另一个字线通过每个单元。

公开(公告)号：US6069819A

公开(公告)日：2000-05-30

申请号：US392679

申请日：1999-09-09

Applicant: Sandip Tiwari

Inventor： Sandip Tiwari

IPC: G11C11/404 ,  H01L21/28 ,  H01L21/8242 ,  H01L27/108 ,  G11C11/24

CPC classification number: H01L27/10873 ,  G11C11/404 ,  H01L21/28273 ,  H01L27/10832 ,  H01L27/10808

Abstract: A memory cell is provided that includes a transistor and a capacitor. The transistor has a gate, a drain, a source, and a back-plane gate, and the capacitor has first and second electrodes. The back-plane gate of the transistor is connected to the first electrode of the capacitor. In a preferred embodiment, the source of the transistor is also connected to the first electrode of the capacitor. Additionally, a memory cell is provided that includes a transistor and a capacitor. The transistor has a gate, a drain, a source, and a back-plane gate, and the capacitor has first and second electrodes. The first electrode of the capacitor is connected to the source of the transistor, and the back-plane gate changes the threshold voltage of the transistor in correspondence to charge stored on the capacitor. In one preferred embodiment, the back-plane gate is charged from the transistor by a tunneling process.

Abstract translation: 提供了包括晶体管和电容器的存储单元。 晶体管具有栅极，漏极，源极和背面栅极，并且电容器具有第一和第二电极。 晶体管的背面栅极连接到电容器的第一电极。 在优选实施例中，晶体管的源极也连接到电容器的第一电极。 另外，提供了包括晶体管和电容器的存储单元。 晶体管具有栅极，漏极，源极和背面栅极，并且电容器具有第一和第二电极。 电容器的第一电极连接到晶体管的源极，并且背面栅极对应于存储在电容器上的电荷来改变晶体管的阈值电压。 在一个优选实施例中，通过隧穿工艺从晶体管充电背板栅极。

公开(公告)号：US5714766A

公开(公告)日：1998-02-03

申请号：US536510

申请日：1995-09-29

Applicant: Wei Chen ,  Theoren Perlee Smith, III ,  Sandip Tiwari

Inventor： Wei Chen ,  Theoren Perlee Smith, III ,  Sandip Tiwari

IPC: H01L27/10 ,  B82B1/00 ,  G11C11/56 ,  G11C16/04 ,  H01L21/336 ,  H01L21/8247 ,  H01L29/06 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  H01L31/0328 ,  H01L31/0336

CPC classification number: H01L21/28273 ,  B82Y10/00 ,  G11C11/5621 ,  G11C11/5642 ,  G11C16/0408 ,  H01L29/66825 ,  H01L29/7887 ,  H01L29/7888 ,  G11C2216/08 ,  Y10S438/962

Abstract: A memory device and memory incorporating a plurality of the memory devices is described wherein each memory device has spaced apart source and drain regions, a channel, a barrier insulating layer, a nanocrystal or a plurality of nanocrystals, a control barrier layer, and a gate electrode. The nanocrystal which may be a quantum dot, stores one electron or hole or a discrete number of electrons or holes at room temperature to provide threshold voltage shifts in excess of the thermal voltage for each change in an electron or a hole stored. The invention utilizes Coulomb blockade in electrostatically coupling one or more stored electrons or holes to a channel while avoiding in-path Coulomb-blockade controlled conduction for sensing the stored charge.

Abstract translation: 一种存储装置和存储器，其中包括多个存储器件，其中每个存储器件具有间隔开的源极和漏极区，通道，阻挡绝缘层，纳米晶体或多个纳米晶体，控制势垒层和栅极 电极。 可以是量子点的纳米晶体在室温下存储一个电子或空穴或离散数量的电子或空穴，以为电子或存储的空穴的每个变化提供超过热电压的阈值电压偏移。 本发明利用库仑阻塞将一个或多个存储的电子或空穴静电耦合到通道，同时避免路径中的库仑阻塞控制传导以感测存储的电荷。

公开(公告)号：US5363397A

公开(公告)日：1994-11-08

申请号：US968109

申请日：1992-10-29

Applicant: Reuben T. Collins ,  Sandip Tiwari

Inventor： Reuben T. Collins ,  Sandip Tiwari

IPC: H01L33/00 ,  G02B6/36 ,  G02B6/42 ,  H01S5/00 ,  H01S5/028 ,  H01S5/10 ,  H01S5/125 ,  H01S5/323 ,  H01S3/06 ,  H01S3/08

CPC classification number: H01S5/028 ,  G02B6/423 ,  H01S5/0207 ,  H01S5/02284 ,  H01S5/0281 ,  H01S5/1039 ,  H01S5/125 ,  H01S5/3202 ,  H01S5/32308 ,  H01S5/32391 ,  H01S5/4031

Abstract: An edge emitting laser combines many of the desirable attributes of the common forms of surface-emitting and edge-emitting laser structures together with elimination of their drawbacks. The laser cavity of a device according to the present invention is short (on the order of the wavelength of light in the cavity medium) and current is injected into the optical cavity substantially perpendicular to the plane of emitted light and parallel to the plane of reflective mirrors. The use of a short optical cavity permits single mode laser operation because of broad mode to mode spacing and large changes in reflectivity between wavelengths. Injecting current into the cavity perpendicular to the direction of light emission provides low power operation because the resistance associated with the injected current is low. The resistance is low because current does not cross boundaries between the different material layers forming the reflective mirrors and the optical cavity. A groove in the semiconductor substrate is formed which aligns an optical fiber to one edge of the laser device. The formation of an optical device incorporating this laser structure is inexpensive to manufacture because the laser is based on planar semiconductor fabrication techniques and the optical alignment of an optical fiber to the laser has been defined by the groove adjacent the laser device.

Abstract translation: 边缘发射激光器结合了许多常见形式的表面发射和边缘发射激光器结构的所需属性，同时消除了它们的缺点。 根据本发明的装置的激光腔是短的（在空腔介质中的光的波长的数量级），并且电流被注入基本上垂直于发射光的平面并平行于反射平面的光腔中 镜子。 使用短的光学腔允许单模激光操作，因为宽模式到模式间隔和波长之间的反射率的大的变化。 注入垂直于光发射方向的空腔中的电流提供低功率操作，因为与注入电流相关联的电阻低。 电阻很低，因为电流不会跨越形成反射镜和光腔的不同材料层之间的边界。 形成半导体衬底中的凹槽，其将光纤对准激光器件的一个边缘。 结合这种激光结构的光学器件的形成制造成本低廉，因为激光器是基于平面半导体制造技术，并且光纤到激光器的光学对准已经由邻近激光器件的凹槽限定。