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118 条记录 (耗时 0.035 秒)

    Current Regulator
    51.
    发明申请
    Current Regulator 审中-公开
    电流调节器

    公开(公告)号：US20130057245A1

    公开(公告)日：2013-03-07

    申请号：US13557793

    申请日：2012-07-25

    申请人： Teppei HIROTSU ,  Nobuyasu Kanekawa ,  Ryosuke Ishida ,  Tsutomu Yamada ,  Chihiro Sato

    发明人： Teppei HIROTSU ,  Nobuyasu Kanekawa ,  Ryosuke Ishida ,  Tsutomu Yamada ,  Chihiro Sato

    IPC分类号： G05F3/02

    CPC分类号： H02M7/53803 ,  H02M3/1588 ,  H02M7/5395 ,  H02M2001/0009 ,  Y02B70/1466

    摘要： A current regulator has a current regulating semiconductor device and a microcontroller which outputs a PWM pulse for driving a load to the current regulating semiconductor device and receives outputs of a high-side current detection circuit and a low-side current detection circuit from the current regulating semiconductor device. An output mixer of the current regulating semiconductor device switches, in synchronization with the PWM pulse, between the output of the high-side current detection circuit and the output of the low-side current detection circuit on one signal line to output the output to the microcontroller.

    摘要翻译： 电流调节器具有电流调节半导体器件和微控制器，其输出用于将负载驱动到电流调节半导体器件的PWM脉冲，并且从电流调节器接收高侧电流检测电路和低侧电流检测电路的输出 半导体器件。 电流调节半导体装置的输出混频器与PWM脉冲同步地在高边电流检测电路的输出和低端电流检测电路的输出之间切换，以将输出输出到 微控制器

    Microcontroller and electronic control unit
    52.
    发明授权
    Microcontroller and electronic control unit 有权
    微控制器和电子控制单元

    公开(公告)号：US08291188B2

    公开(公告)日：2012-10-16

    申请号：US12706938

    申请日：2010-02-17

    申请人： Hiromichi Yamada ,  Yuichi Ishiguro ,  Nobuyasu Kanekawa

    发明人： Hiromichi Yamada ,  Yuichi Ishiguro ,  Nobuyasu Kanekawa

    IPC分类号： G06F12/12

    CPC分类号： G06F11/1641 ,  G06F11/1683

    摘要： A microcontroller in which respective CPUs execute different applications so as to improve processing performance, and the respective CPUs execute an application that requires safety and mutually compare the results thereof so as to enhance the reliability of write data is provided. The microcontroller has a plurality of processing systems made up of a first CPU, a second CPU, a first memory and a second memory, and for the instruction processing about specific processing set in advance, the write to peripheral modules which are not multiplexed is executed twice, and the write data of the first time and the second time are mutually collated.

    摘要翻译： 其中相应CPU执行不同应用以提高处理性能的微控制器，并且相应的CPU执行需要安全性并相互比较其结果的应用，以提供写入数据的可靠性。 微控制器具有由第一CPU，第二CPU，第一存储器和第二存储器构成的多个处理系统，并且对于关于预先设定的特定处理的指令处理，执行未复用的对外围模块的写入 两次，并且第一次和第二次的写入数据被相互整理。

    Brushless motor system
    53.
    发明授权
    Brushless motor system 有权
    无刷电机系统

    公开(公告)号：US08198847B2

    公开(公告)日：2012-06-12

    申请号：US12638045

    申请日：2009-12-15

    申请人： Tadahiko Chida ,  Akira Mishima ,  Nobuyasu Kanekawa

    发明人： Tadahiko Chida ,  Akira Mishima ,  Nobuyasu Kanekawa

    IPC分类号： G05B5/00

    CPC分类号： H02M1/126 ,  H02P29/50

    摘要： A brushless motor system which can suppress adverse influences of electromagnetic noise without increasing the size and enhancing the performance of a filter circuit. In a brushless motor system comprising a brushless motor, an inverter, and a direct current power source, a noise return line for returning a noise current is connected between the brushless motor and the inverter. The noise current is generated in the inverter and reaches the brushless motor. With the provision of the noise return line, a common mode current leaking from the brushless motor to a ground can be reduced.

    摘要翻译： 一种无刷电机系统，可以抑制电磁噪声的不利影响，而不会增加滤波电路的尺寸，提高滤波电路的性能。 在包括无刷电动机，逆变器和直流电源的无刷电动机系统中，用于返回噪声电流的噪声返回线连接在无刷电动机和逆变器之间。 在变频器中产生噪声电流并到达无刷电机。 通过设置噪声回馈线，可以减少从无刷电动机泄漏到地面的共模电流。

    Resolver/digital converter and control apparatus using the same
    56.
    发明授权
    Resolver/digital converter and control apparatus using the same 有权
    转换器/数字转换器及使用其的控制装置

    公开(公告)号：US07009535B2

    公开(公告)日：2006-03-07

    申请号：US11211506

    申请日：2005-08-26

    申请人： Nobuyasu Kanekawa ,  Shoji Sasaki ,  Katsuya Oyama ,  Tomonobu Koseki

    发明人： Nobuyasu Kanekawa ,  Shoji Sasaki ,  Katsuya Oyama ,  Tomonobu Koseki

    IPC分类号： H03M1/48 ,  G06F11/30

    CPC分类号： B60T8/885 ,  B60T2270/402 ,  B62D5/0481 ,  G01D5/2073 ,  G05B9/02 ,  H03M1/1076 ,  H03M1/645

    摘要： This resolver/digital converter has a resolver, a resolver/digital converting portion and an exciting signal generator. The exciting signal generated from the exciting signal generator is supplied to the resolver, and the resolver signals produced from the resolver are supplied to the resolver/digital converter. This resolver/digital converter further has a conversion trigger generator that generates a conversion trigger signal on the basis of the exciting signal generated from the exciting signal generator, an A/D converter that converts the resolver signals produced from the resolver to digital values in response to the conversion trigger signal generated from the conversion trigger generator, and computing means that detects the failure status on the basis of the digital values produced from the A/D converter.

    摘要翻译： 该解算器/数字转换器具有分解器，分解器/数字转换部分和激励信号发生器。 从激励信号发生器产生的激励信号被提供给解算器，并且从分解器产生的解算器信号被提供给解算器/数字转换器。 该解算器/数字转换器还具有转换触发发生器，其基于从激励信号发生器产生的激励信号产生转换触发信号，A / D转换器将从分解器产生的分解器信号转换为数字值 涉及从转换触发发生器产生的转换触发信号，以及基于从A / D转换器产生的数字值来检测故障状态的计算装置。

    Logic circuit having error detection function, redundant resource management method, and fault tolerant system using it
    59.
    发明授权
    Logic circuit having error detection function, redundant resource management method, and fault tolerant system using it 失效
    具有错误检测功能的逻辑电路，冗余资源管理方法和使用它的容错系统

    公开(公告)号：US06513131B1

    公开(公告)日：2003-01-28

    申请号：US09376008

    申请日：1999-08-19

    申请人： Nobuyasu Kanekawa ,  Shoji Suzuki ,  Yoshimichi Sato ,  Korefumi Tashiro ,  Keisuke Bekki ,  Hiroshi Sato ,  Makoto Nohmi ,  Shinya Ohtsuji

    发明人： Nobuyasu Kanekawa ,  Shoji Suzuki ,  Yoshimichi Sato ,  Korefumi Tashiro ,  Keisuke Bekki ,  Hiroshi Sato ,  Makoto Nohmi ,  Shinya Ohtsuji

    IPC分类号： G06F702

    CPC分类号： G06F11/0763 ,  G05B9/03 ,  G06F11/008 ,  G06F11/0796 ,  G06F11/085 ,  G06F11/1695 ,  G06F11/18 ,  G06F11/188 ,  G06F11/2023 ,  G06F11/2035 ,  G06F11/2215

    摘要： A self-checking circuit, which is useful for a highly reliable system configuration, includes a logic circuit having an error detection function. For function blocks for feeding out a plurality of signals that are at least duplexed, the logic circuit compares the output signals of the function blocks, and detects an error on the basis of results of the comparison. The logic circuit comprises synthesizing means provided to superimpose inherent waveforms assigned in advance to the respective output signals of the function blocks onto the output signals of one of the function blocks. The inherent waveforms are orthogonal waveforms generated by an orthogonal waveform generator circuit. The logic circuit also comprises comparison means for comparing a signal output of the synthesizing means with the signal output of the other function block to detect an error. The whole circuit including the function blocks are judged normal only if the waveforms inherent to both output signals exist.

    摘要翻译： 对于高度可靠的系统配置有用的自检电路包括具有错误检测功能的逻辑电路。 对于用于输出至少双工的多个信号的功能块，逻辑电路比较功能块的输出信号，并且基于比较的结果来检测错误。 逻辑电路包括合成装置，用于将预先分配的固有波形与功能块的各个输出信号叠加到一个功能块的输出信号上。 固有波形是由正交波形发生器电路产生的正交波形。 逻辑电路还包括比较装置，用于将合成装置的信号输出与另一功能块的信号输出进行比较，以检测误差。 包括功能块的整个电路仅在存在两个输出信号固有的波形时才被判断为正常。

    Signal transmission apparatus using an isolator, modem, and information processor
    60.
    发明授权
    Signal transmission apparatus using an isolator, modem, and information processor 失效
    使用隔离器，调制解调器和信息处理器的信号传输装置

    公开(公告)号：US06389063B1

    公开(公告)日：2002-05-14

    申请号：US09182219

    申请日：1998-10-30

    申请人： Nobuyasu Kanekawa ,  Kazuo Kato ,  Yasuyuki Kojima ,  Seigoh Yukitake

    发明人： Nobuyasu Kanekawa ,  Kazuo Kato ,  Yasuyuki Kojima ,  Seigoh Yukitake

    IPC分类号： H04B138

    CPC分类号： H04L1/0041 ,  H04L1/0045 ,  H04L25/0266

    摘要： The signal x to be transmitted is converted to the redundant code f(x) by the redundancy coder 6 and transmitted via the isolating capacitor 2 of the isolator 50. When the signal f(x) redundancy-coded and transmitted is the coded word f(xi), the decoder 7 outputs xi which is inferred as an equivalent original signal and when an error occurs and the signal f(x) does not match the coded word f(xi), the decoder 7 corrects the error and outputs xi which is inferred as an original signal.

    摘要翻译： 要发送的信号x被冗余编码器6转换成冗余码f（x），并通过隔离器50的隔离电容器2传输。当冗余编码和发送的信号f（x）是编码字f （xi）中，解码器7输出被推定为等效原始信号的xi，并且当出现错误并且信号f（x）与编码字f（xi）不匹配时，解码器7校正误差并输出xi，其中 被推断为原始信号。