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公开(公告)号：US20130087767A1
公开(公告)日：2013-04-11
申请号：US13270648
申请日：2011-10-11
CPC分类号： H01L51/0048 , B82Y10/00 , H01L29/0673 , H01L29/42384 , H01L29/42392 , H01L29/775 , H01L51/055 , H01L51/102 , Y10S977/742 , Y10S977/938
摘要： A structure includes a substrate having a carbon nanotube (CNT) disposed over a surface. The CNT is partially disposed within a protective electrically insulating layer. The structure further includes a gate stack disposed over the substrate. A first portion of a length of the CNT not covered by the protective electrically insulating layer passes through the gate stack. Source and drain contacts are disposed adjacent to the gate stack, where second and third portions of the length of CNT not covered by the protective electrically insulating layer are conductively electrically coupled to the source and drain contacts. The gate stack and the source and drain contacts are contained within the protective electrically insulating layer and within an electrically insulating organic planarization layer that is disposed over the protective electrically insulating layer. A method to fabricate a CNT-based transistor is also described.
摘要翻译： 结构包括具有设置在表面上的碳纳米管（CNT）的基板。 CNT部分地设置在保护性电绝缘层内。 该结构还包括设置在衬底上的栅极堆叠。 未被保护电绝缘层覆盖的CNT的长度的第一部分通过栅极堆叠。 源极和漏极触点设置成与栅极堆叠相邻，其中未被保护电绝缘层覆盖的CNT的长度的第二和第三部分导电地电耦合到源极和漏极触点。 栅极堆叠以及源极和漏极触点包含在保护电绝缘层内并且设置在保护性电绝缘层之上的电绝缘的有机平坦化层内。 还描述了制造CNT基晶体管的方法。
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52.发明授权Field-effect transistor device having a metal gate stack with an oxygen barrier layer 有权具有具有氧阻隔层的金属栅叠层的场效应晶体管器件公开(公告)号：US08415677B2
公开(公告)日：2013-04-09
申请号：US12690178
申请日：2010-01-20
申请人： Praneet Adusumilli , Alessandro Callegari , Josephine B. Chang , Changhwan Choi , Martin Michael Frank , Michael A. Guillorn , Vijay Narayanan
发明人： Praneet Adusumilli , Alessandro Callegari , Josephine B. Chang , Changhwan Choi , Martin Michael Frank , Michael A. Guillorn , Vijay Narayanan
IPC分类号： H01L29/04
CPC分类号： H01L29/4966 , H01L21/28088 , H01L29/513
摘要： A field effect transistor device and method which includes a semiconductor substrate, a dielectric gate layer, preferably a high dielectric constant gate layer, overlaying the semiconductor substrate and an electrically conductive oxygen barrier layer overlaying the gate dielectric layer. In one embodiment, there is a conductive layer between the gate dielectric layer and the oxygen barrier layer. In another embodiment, there is a low resistivity metal layer on the oxygen barrier layer.
摘要翻译： 一种场效应晶体管器件和方法，其包括覆盖半导体衬底的半导体衬底，介电栅极层，优选高介电常数栅极层和覆盖栅极电介质层的导电氧阻挡层。 在一个实施例中，在栅介质层和氧阻挡层之间存在导电层。 在另一个实施例中，在氧阻隔层上存在低电阻率金属层。
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公开(公告)号：US08288236B2
公开(公告)日：2012-10-16
申请号：US13345252
申请日：2012-01-06
IPC分类号： H01L21/336
CPC分类号： H01L51/001 , B82Y10/00 , H01L51/0048 , H01L51/0541 , H01L51/0558
摘要： A field effect transistor (FET) includes a drain formed of a first material, a source formed of the first material, a channel formed by a nanostructure coupling the source to the drain, and a gate formed between the source and the drain and surrounding the nanostructure.
摘要翻译： 场效应晶体管（FET）包括由第一材料形成的漏极，由第一材料形成的源极，由将源极耦合到漏极的纳米结构形成的沟道以及在源极和漏极之间形成的栅极， 纳米结构。
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公开(公告)号：US20120256242A1
公开(公告)日：2012-10-11
申请号：US13080390
申请日：2011-04-05
CPC分类号： H01L27/1203 , B82Y10/00 , H01L21/84 , H01L29/0673 , H01L29/42392 , H01L29/78696
摘要： An integrated circuit apparatus is provided and includes first and second silicon-on-insulator (SOI) pads formed on an insulator substrate, each of the first and second SOI pads including an active area formed thereon, a nanowire suspended between the first and second SOI pads over the insulator substrate, one or more field effect transistors (FETs) operably disposed along the nanowire and a planar device operably disposed on at least one of the respective active areas formed on each of the first and second SOI pads.
摘要翻译： 提供一种集成电路装置，其包括形成在绝缘体基板上的第一和第二绝缘体上硅（SOI）焊盘，第一和第二SOI焊盘中的每一个包括形成在其上的有源区，悬挂在第一和第二SOI之间的纳米线 绝缘体衬底上的衬垫，沿着纳米线可操作地设置的一个或多个场效应晶体管（FET）和可操作地设置在形成在每个第一和第二SOI衬垫上的相应有源区域中的至少一个上的平面器件。
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公开(公告)号：US20120235234A1
公开(公告)日：2012-09-20
申请号：US13047132
申请日：2011-03-14
IPC分类号： H01L29/78 , H01L21/3205 , B82Y99/00
CPC分类号： H01L29/66545 , B82Y10/00 , H01L27/1211 , H01L29/66795 , H01L29/7855
摘要： A FinFET device with an independent control gate, including: a silicon-on-insulator substrate; a non-planar multi-gate transistor disposed on the silicon-on-insulator substrate, the transistor comprising a conducting channel wrapped around a thin silicon fin; a source/drain extension region; an independently addressable control gate that is self-aligned to the fin and does not extend beyond the source/drain extension region, the control gate comprising: a thin layer of silicon nitride; and a plurality of spacers.
摘要翻译： 一种具有独立控制栅极的FinFET器件，包括：绝缘体上硅衬底; 设置在绝缘体上硅衬底上的非平面多栅极晶体管，所述晶体管包括围绕薄硅片缠绕的导电沟道; 源极/漏极延伸区域; 独立可寻址的控制栅极，其与所述鳍片自对准并且不延伸超过所述源极/漏极延伸区域，所述控制栅极包括：氮化硅薄层; 和多个间隔件。
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公开(公告)号：US20120195102A1
公开(公告)日：2012-08-02
申请号：US13015936
申请日：2011-01-28
CPC分类号： G11C11/404 , B82Y10/00 , G11C23/00 , H01L27/108 , H01L27/10861 , H01L28/82 , H01L28/86 , H01L29/0673 , H01L29/84 , Y10T29/4913
摘要： A DRAM cell and method for storing information in a dynamic random access memory using an electrostatic actuator beam to make an electrical connection between a storage capacitor and a bit line.
摘要翻译： 一种用于使用静电致动器光束在动态随机存取存储器中存储信息以在存储电容器和位线之间形成电连接的DRAM单元和方法。
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57.发明申请FIELD-EFFECT TRANSISTOR DEVICE HAVING A METAL GATE STACK WITH AN OXYGEN BARRIER LAYER 有权具有氧阻挡层的金属栅极堆叠的场效应晶体管器件公开(公告)号：US20110175147A1
公开(公告)日：2011-07-21
申请号：US12690178
申请日：2010-01-20
申请人： Praneet Adusumilli , Alessandro Callegari , Josephine B. Chang , Changhwan Choi , Martin M. Frank , Michael A. Guillorn , Vijay Narayanan
发明人： Praneet Adusumilli , Alessandro Callegari , Josephine B. Chang , Changhwan Choi , Martin M. Frank , Michael A. Guillorn , Vijay Narayanan
CPC分类号： H01L29/4966 , H01L21/28088 , H01L29/513
摘要： A field effect transistor device and method which includes a semiconductor substrate, a dielectric gate layer, preferably a high dielectric constant gate layer, overlaying the semiconductor substrate and an electrically conductive oxygen barrier layer overlaying the gate dielectric layer. In one embodiment, there is a conductive layer between the gate dielectric layer and the oxygen barrier layer. In another embodiment, there is a low resistivity metal layer on the oxygen barrier layer.
摘要翻译： 一种场效应晶体管器件和方法，其包括覆盖半导体衬底的半导体衬底，介电栅极层，优选高介电常数栅极层和覆盖栅极电介质层的导电氧阻挡层。 在一个实施例中，在栅介质层和氧阻挡层之间存在导电层。 在另一个实施例中，在氧阻隔层上存在低电阻率金属层。
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公开(公告)号：US20110127493A1
公开(公告)日：2011-06-02
申请号：US12627120
申请日：2009-11-30
申请人： Cyril Cabral, JR. , Josephine B. Chang , Alfred Grill , Michael A. Guillorn , Christian Lavoie , Eugene J. O'Sullivan
发明人： Cyril Cabral, JR. , Josephine B. Chang , Alfred Grill , Michael A. Guillorn , Christian Lavoie , Eugene J. O'Sullivan
IPC分类号： H01L29/66 , H01L21/336
CPC分类号： H01L29/775 , B82Y10/00 , H01L29/16 , H01L29/1602 , H01L51/0048 , H01L51/0541 , H01L51/105
摘要： A field effect transistor includes a metal carbide source portion, a metal carbide drain portion, an insulating carbon portion separating the metal carbide source portion from the metal carbide portion, a nanostructure formed over the insulating and carbon portion and connecting the metal carbide source portion to the metal carbide drain portion, and a gate stack formed on over at least a portion of the insulating carbon portion and at least a portion of the nanostructure.
摘要翻译： 场效应晶体管包括金属碳化物源部分，金属碳化物漏极部分，将金属碳化物源部分与金属碳化物部分分离的绝缘碳部分，形成在绝缘和碳部分上的纳米结构，并将金属碳化物源部分连接到 金属碳化物排出部分和形成在绝缘碳部分的至少一部分和至少一部分纳米结构上的栅堆叠。
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公开(公告)号：US20110073909A1
公开(公告)日：2011-03-31
申请号：US12567963
申请日：2009-09-28
IPC分类号： H01L29/772 , H01L21/335 , H01L21/203
CPC分类号： H01L29/7391 , H01L29/66356
摘要： A semiconductor fabrication method includes depositing a dummy gate layer onto a substrate, patterning the dummy gate layer, depositing a hardmask layer over the dummy gate layer, patterning the hardmask layer, etching a recess into the substrate, adjacent the dummy gate layer, depositing a semiconductor material into the recess, removing the hardmask layer, depositing replacement spacers onto the dummy gate layer, performing an oxide deposition over the dummy gate layer and replacement spacers, removing the dummy gate and replacement spacers, thereby forming a gate recess in the oxide and depositing a gate stack into the recess.
摘要翻译： 一种半导体制造方法，包括在基板上沉积虚拟栅极层，图案化虚拟栅极层，在伪栅极层上沉积硬掩模层，图案化硬掩模层，在凹模栅极层附近蚀刻到衬底中的凹陷， 将半导体材料进入凹部，去除硬掩模层，将替代间隔物沉积到伪栅极层上，在伪栅极层和替换间隔物上进行氧化物沉积，去除伪栅极和替换间隔物，从而在氧化物中形成栅极凹槽， 将栅极堆叠沉积到凹槽中。
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公开(公告)号：US07892945B2
公开(公告)日：2011-02-22
申请号：US12848582
申请日：2010-08-02
IPC分类号： H01L21/76
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/66772 , H01L29/66795 , H01L29/775 , H01L29/785 , H01L29/78696 , Y10S977/72 , Y10S977/742 , Y10S977/762 , Y10S977/938
摘要： A semiconductor structure is provided that includes a plurality of vertically stacked and vertically spaced apart semiconductor nanowires (e.g., a semiconductor nanowire mesh) located on a surface of a substrate. One end segment of each vertically stacked and vertically spaced apart semiconductor nanowires is connected to a source region and another end segment of each vertically stacked and vertically spaced apart semiconductor nanowires is connected to a drain region. A gate region including a gate dielectric and a gate conductor abuts the plurality of vertically stacked and vertically spaced apart semiconductor nanowires, and the source regions and the drain regions are self-aligned with the gate region.
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