公开(公告)号：US20140061737A1

公开(公告)日：2014-03-06

申请号：US13598275

申请日：2012-08-29

Applicant: Wen-I Hsu ,  Min-Feng Kao ,  Jen-Cheng Liu ,  Dun-Nian Yaung ,  Tzu-Hsuan Hsu ,  Wen-De Wang

Inventor： Wen-I Hsu ,  Min-Feng Kao ,  Jen-Cheng Liu ,  Dun-Nian Yaung ,  Tzu-Hsuan Hsu ,  Wen-De Wang

IPC: H01L27/146 ,  H01L31/18 ,  H01L27/088

CPC classification number: H01L27/14689 ,  H01L21/761 ,  H01L21/76237 ,  H01L27/1463 ,  H01L27/14643 ,  H01L29/0649

Abstract: A system and method for isolating semiconductor devices is provided. An embodiment comprises an isolation region that is laterally removed from source/drain regions of semiconductor devices and has a dielectric material extending over the isolation implant between the source/drain regions. The isolation region may be formed by forming an opening through a layer over the substrate, depositing a dielectric material along the sidewalls of the opening, implanting ions into the substrate after the deposition, and filling the opening with another dielectric material.

Abstract translation: 提供一种用于隔离半导体器件的系统和方法。 一个实施例包括从半导体器件的源极/漏极区域侧向移除的隔离区域，并且具有在源极/漏极区域之间的隔离注入物上延伸的介电材料。 可以通过在衬底上形成通过层的开口形成隔离区域，沿着开口的侧壁沉积电介质材料，在沉积之后将离子注入到衬底中，并用另一种电介质材料填充该开口。

公开(公告)号：US08325530B2

公开(公告)日：2012-12-04

申请号：US11542749

申请日：2006-10-03

Applicant: Hang-Ting Lue ,  Tzu-Hsuan Hsu ,  Erh-Kun Lai

Inventor： Hang-Ting Lue ,  Tzu-Hsuan Hsu ,  Erh-Kun Lai

IPC: G11C11/34

CPC classification number: G11C16/10 ,  G11C16/0416 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/7851 ,  H01L29/7883

Abstract: A method of performing an operation on a flash memory cell device, used when a gate coupling ratio between a floating gate and a control gate of less than 0.4. A potential is required to be applied across the control gate. Electrons are either injected to the floating gate from the control gate or ejected from the floating gate to the control gate. The operation associated with the injection or the ejection is determined by the nature of a silicon channel provided in the device. Devices using a bulk-tied FinFET-like structure are particularly suited to this method. The method is also particularly suited for use on cells in a NAND array.

Abstract translation: 在浮动栅极和控制栅极之间的栅极耦合比小于0.4时使用的对闪存单元器件进行操作的方法。 需要在控制门上施加电位。 电子从控制栅极注入到浮动栅极或从浮动栅极喷射到控制栅极。 与注射或喷射相关联的操作由设备中提供的硅通道的性质决定。 使用大容量FinFET类结构的器件特别适用于该方法。 该方法还特别适用于NAND阵列中的单元。

公开(公告)号：US20120038017A1

公开(公告)日：2012-02-16

申请号：US13271780

申请日：2011-10-12

Applicant: Tzu-Hsuan Hsu ,  Dun-Nian Yaung

Inventor： Tzu-Hsuan Hsu ,  Dun-Nian Yaung

IPC: H01L31/02

CPC classification number: H01L27/14645 ,  H01L27/1464

Abstract: A method of making a backside illuminated sensor is provided. A substrate is provided and a high energy ion implantation is performed over the substrate to implant a first doped region. A layer is formed over the substrate and a self-align high energy ion implantation is performed over the substrate to implant a second doped region over the first doped region. The combined thickness of the first and second doped region is greater than 50 percent of thickness of the substrate and the distance between back surface of the substrate and the first and second doped regions is less than 50 percent of thickness of the substrate. In this way, an enlarged light sensing region is formed through which electrons generated from back surface of the surface may easily reach the pixel.

Abstract translation: 提供制造背面照明传感器的方法。 提供衬底并且在衬底上执行高能离子注入以注入第一掺杂区域。 在衬底上形成层，并在衬底上执行自对准高能离子注入，以在第一掺杂区域上注入第二掺杂区域。 第一和第二掺杂区域的组合厚度大于衬底的厚度的50％，并且衬底的背表面与第一和第二掺杂区域之间的距离小于衬底厚度的50％。 以这种方式，形成放大的光感测区域，通过该放大的光感测区域从表面的后表面产生的电子可以容易地到达像素。

公开(公告)号：US07855411B2

公开(公告)日：2010-12-21

申请号：US11958134

申请日：2007-12-17

Applicant: Tzu-Hsuan Hsu ,  Hang-Ting Lue

Inventor： Tzu-Hsuan Hsu ,  Hang-Ting Lue

IPC: H01L29/792

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L21/84 ,  H01L27/115 ,  H01L27/12 ,  H01L29/66833 ,  H01L29/792

Abstract: The invention provides a memory cell. The memory cell is disposed on a substrate and comprises a plurality of isolation structures defining at least a fin structure in the substrate. Further, the surface of the fin structure is higher than the surface of the isolation structure. The memory cell comprises a doped region, a gate, a charge trapping structure and a source/drain region. The doped region is located in a top of the fin structure and near a surface of the top of the fin structure and the doped region has a first conductive type. The gate is disposed on the substrate and straddled the fin structure. The charge trapping structure is disposed between the gate and the fin structure. The source/drain region with a second conductive type is disposed in the fin structures exposed by the gate and the first conductive type is different from the second conductive type.

Abstract translation: 本发明提供一种存储单元。 存储单元设置在基板上并且包括在基板中限定至少鳍结构的多个隔离结构。 此外，翅片结构的表面高于隔离结构的表面。 存储单元包括掺杂区域，栅极，电荷俘获结构和源极/漏极区域。 掺杂区域位于鳍结构的顶部并且在鳍结构的顶部的表面附近，并且掺杂区域具有第一导电类型。 栅极设置在基板上并跨越翅片结构。 电荷捕获结构设置在栅极和鳍结构之间。 具有第二导电类型的源极/漏极区域设置在由栅极暴露的鳍状结构中，并且第一导电类型不同于第二导电类型。

公开(公告)号：US20100311217A1

公开(公告)日：2010-12-09

申请号：US12818057

申请日：2010-06-17

Applicant: Chao-I Wu ,  Tzu-Hsuan Hsu ,  Hang-Ting Lue ,  Erh-Kun Lai

Inventor： Chao-I Wu ,  Tzu-Hsuan Hsu ,  Hang-Ting Lue ,  Erh-Kun Lai

IPC: H01L21/336

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/513

Abstract: A non-volatile memory cell may include a semiconductor substrate; a source region in a portion of the substrate; a drain region within a portion of the substrate; a well region within a portion of the substrate. The memory cell may further include a first carrier tunneling layer over the substrate; a charge storage layer over the first carrier tunneling layer; a second carrier tunneling layer over the charge storage layer; and a conductive control gate over the second carrier tunneling layer. Specifically, the drain region is spaced apart from the source region, and the well region may surround at least a portion of the source and drain regions. In one example, the second carrier tunneling layer provides hole tunneling during an erasing operation and may include at least one dielectric layer.

Abstract translation: 非易失性存储单元可以包括半导体衬底; 在所述基板的一部分中的源极区域; 在所述衬底的一部分内的漏区; 衬底的一部分内的阱区。 存储单元还可以包括在衬底上的第一载流子隧穿层; 第一载流子隧道层上的电荷存储层; 电荷存储层上的第二载流子隧穿层; 以及在所述第二载流子隧穿层上的导电控制栅极。 具体地，漏极区域与源极区域间隔开，并且阱区域可以围绕源极和漏极区域的至少一部分。 在一个示例中，第二载流子隧道层在擦除操作期间提供空穴隧穿，并且可以包括至少一个电介质层。

公开(公告)号：US07803647B2

公开(公告)日：2010-09-28

申请号：US11672681

申请日：2007-02-08

Applicant: Wen-De Wang ,  Dun-Nian Yaung ,  Tzu-Hsuan Hsu ,  Shine Chung

Inventor： Wen-De Wang ,  Dun-Nian Yaung ,  Tzu-Hsuan Hsu ,  Shine Chung

IPC: H01L21/00

CPC classification number: H01L27/14632 ,  H01L27/14625 ,  H01L27/14687

Abstract: The present disclosure provides an image sensor semiconductor device. The semiconductor device includes a sensor element disposed in a semiconductor substrate; an inter-level dielectric (ILD) disposed on the semiconductor substrate; and a trench disposed in the ILD, overlying and enclosing the sensor element, and filled with a first dielectric material.

Abstract translation: 本公开提供了一种图像传感器半导体器件。 半导体器件包括设置在半导体衬底中的传感器元件; 布置在所述半导体衬底上的级间电介质（ILD）; 以及设置在ILD中的沟槽，覆盖并封闭传感器元件，并且填充有第一介电材料。

公开(公告)号：US07799654B2

公开(公告)日：2010-09-21

申请号：US11291880

申请日：2005-12-01

Applicant: Yuan-Chih Hsieh ,  Chung-Yi Yu ,  Tsung-Hsun Huang ,  Tzu-Hsuan Hsu ,  Chia-Shiung Tsai

Inventor： Yuan-Chih Hsieh ,  Chung-Yi Yu ,  Tsung-Hsun Huang ,  Tzu-Hsuan Hsu ,  Chia-Shiung Tsai

IPC: H01L21/76 ,  H01L31/062 ,  H01L31/111 ,  H01L27/148 ,  H01L29/768

CPC classification number: H01L27/14632 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14687

Abstract: An image sensor device includes a semiconductor substrate and a plurality of pixels on the substrate. An etch-stop layer is formed over the pixels and has a thickness less than about 600 Angstroms. The image sensor device further includes an interlayer dielectric (ILD) overlying the etch stop layer. The etch-stop layer has a refractive index less than about 2 and an extinction coefficient less than about 0.1.

Abstract translation: 图像传感器装置包括半导体衬底和衬底上的多个像素。 在像素上方形成蚀刻停止层，其厚度小于约600埃。 图像传感器装置还包括覆盖在蚀刻停止层上的层间电介质（ILD）。 蚀刻停止层的折射率小于约2，消光系数小于约0.1。

公开(公告)号：US20090039452A1

公开(公告)日：2009-02-12

申请号：US11835814

申请日：2007-08-08

Applicant: Yuan-Chih Hsieh ,  Shih-Chang Liu ,  Shih-Chi Fu ,  Tzu-Hsuan Hsu ,  Chung-Yi Yu ,  Gwo-Yuh Shiau ,  Chia-Shiung Tsai

Inventor： Yuan-Chih Hsieh ,  Shih-Chang Liu ,  Shih-Chi Fu ,  Tzu-Hsuan Hsu ,  Chung-Yi Yu ,  Gwo-Yuh Shiau ,  Chia-Shiung Tsai

IPC: H01L31/00

CPC classification number: H01L27/14643 ,  H01L24/05 ,  H01L27/14636 ,  H01L2224/05556 ,  H01L2924/12043 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor substrate having a front surface and a back surface, elements formed on the substrate, interconnect metal layers formed over the front surface of the substrate, including a topmost interconnect metal layer, an inter-metal dielectric for insulating each of the plurality of interconnect metal layers, and a bonding pad disposed within the inter-metal dielectric, the bonding pad in contact with one of the interconnect metal layers other than the topmost interconnect metal layer.

Abstract translation: 半导体器件包括具有前表面和后表面的半导体衬底，形成在衬底上的元件，形成在衬底的前表面上的互连金属层，包括最上面的互连金属层，用于绝缘的金属间电介质 所述多个互连金属层和设置在所述金属间电介质内的接合焊盘，所述接合焊盘与所述互连金属层中的一个互连金属层之外的最上面的互连金属层接触。

公开(公告)号：US20080087946A1

公开(公告)日：2008-04-17

申请号：US11545575

申请日：2006-10-11

Applicant: Tzu-Hsuan Hsu ,  Yen-Hao Shih ,  Chia-Wei Wu

Inventor： Tzu-Hsuan Hsu ,  Yen-Hao Shih ,  Chia-Wei Wu

IPC: H01L29/76

CPC classification number: H01L29/792 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/1203 ,  H01L29/42352

Abstract: A vertical channel transistor structure is provided. The structure includes a substrate, a channel, a cap layer, a charge trapping layer, a source and a drain. The channel is protruded from the substrate. The cap layer is deposited on the channel. The cap layer and the channel substantially have the same width. The charge trapping layer is deposited on the cap layer and on two vertical surfaces of the channel. The gate is deposited on the charge trapping layer and on two vertical surfaces of the channel. The source and the drain are respectively positioned on two sides of the channel and opposing to the gate.

Abstract translation: 提供了垂直沟道晶体管结构。 该结构包括基板，通道，盖层，电荷捕获层，源极和漏极。 通道从基板突出。 盖层沉积在通道上。 盖层和通道基本上具有相同的宽度。 电荷捕获层沉积在封盖层上和通道的两个垂直表面上。 栅极沉积在电荷捕获层上和通道的两个垂直表面上。 源极和漏极分别位于通道的两侧并与栅极相对。

公开(公告)号：US07301219B2

公开(公告)日：2007-11-27

申请号：US11146777

申请日：2005-06-06

Applicant: Tzu-Hsuan Hsu ,  Yen-Hao Shih ,  Ming-Hsiu Lee

Inventor： Tzu-Hsuan Hsu ,  Yen-Hao Shih ,  Ming-Hsiu Lee

IPC: H01L29/00 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L29/7885 ,  H01L29/7887 ,  H01L29/7923 ,  Y10S257/90

Abstract: An asymmetrically doped memory cell has first and second N+ doped junctions on a P substrate. A composite charge trapping layer is disposed over the P substrate and between the first and the second N+ doped junctions. A N− doped region is positioned adjacent to the first N+ doped junction and under the composite charge trapping layer. A P− doped region is positioned adjacent to the second N+ doped junction and under the composite charge trapping layer. The asymmetrically doped memory cell will store charges at the end of the composite charge trapping layer that is above the P− doped region. The asymmetrically doped memory cell can function as an electrically erasable programmable read only memory cell, and is capable of multiple level cell operations. A method for making an asymmetrically doped memory cell is also described.

Abstract translation: 不对称掺杂的存储单元在P衬底上具有第一和第二N +掺杂结。 复合电荷捕获层设置在P衬底上并且在第一和第二N +掺杂结之间。 N掺杂区域邻近第一N +掺杂结并位于复合电荷俘获层下方。 P-掺杂区域邻近第二N +掺杂结并位于复合电荷俘获层下方。 非对称掺杂的存储单元将在复合电荷捕获层的末端在P掺杂区域之上存储电荷。 非对称掺杂的存储单元可以用作电可擦除可编程只读存储器单元，并且能够进行多级单元操作。 还描述了制造非对称掺杂的存储单元的方法。