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    Method for forming a selective contact and local interconnect in situ and semiconductor devices carrying the same
    51.
    发明授权
    Method for forming a selective contact and local interconnect in situ and semiconductor devices carrying the same 失效
    用于形成选择性接触和局部互连原位以及携带其的半导体器件的方法

    公开(公告)号：US06372643B1

    公开(公告)日：2002-04-16

    申请号：US09056309

    申请日：1998-04-07

    Applicant: Christopher W. Hill ,  Weimin Li ,  Gurtej S. Sandhu

    Inventor： Christopher W. Hill ,  Weimin Li ,  Gurtej S. Sandhu

    IPC: H01L2144

    CPC classification number: H01L21/28568 ,  C23C16/0272 ,  C23C16/44 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76877

    Abstract: A process for the in situ formation of a selective contact and a local interconnect on a semiconductor substrate. The exposed semiconductor substrate regions of a semiconductor device structure may be treated in a plasma to enhance the adhesiveness of a selective contact thereto. The semiconductor device structure is positioned within a reaction chamber, wherein a selective contact is deposited onto the exposed semiconductor substrate regions, Any residual selective contact material may be removed from oxide surfaces either intermediately or after selective contact deposition. While the semiconductor device remains in the reaction chamber, a local interconnect is deposited over the semiconductor device structure. The local interconnect may then be patterned. Subsequent layers may be deposited over the local interconnect. The present invention also includes semiconductor device structures formed by the inventive process.

    Abstract translation: 用于在半导体衬底上原位形成选择性接触和局部互连的方法。 可以在等离子体中处理半导体器件结构的暴露的半导体衬底区域以增强与其的选择性接触的粘合性。 半导体器件结构位于反应室内，其中选择性接触沉积在暴露的半导体衬底区域上。任何残留的选择性接触材料可以在中间或选择性接触沉积之后从氧化物表面去除。 当半导体器件保留在反应室中时，在半导体器件结构上沉积局部互连。 然后可以对局部互连进行图案化。 随后的层可以沉积在局部互连上。 本发明还包括通过本发明方法形成的半导体器件结构。

    Semiconductor structure including metal nitride and metal silicide
    52.
    发明授权
    Semiconductor structure including metal nitride and metal silicide 失效
    半导体结构包括金属氮化物和金属硅化物

    公开(公告)号：US06326668B1

    公开(公告)日：2001-12-04

    申请号：US09285573

    申请日：1999-04-02

    Applicant: Weimin Li

    Inventor： Weimin Li

    IPC: H01L2976

    CPC classification number: H01L21/76855 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76859

    Abstract: The present invention relates to a semiconductor structure including metal nitride and metal silicide, where a metal silicide layer is formed upon an active area that is part of a junction in order to facilitate further miniaturization that is demanded and dictated by the need for smaller devices. A single PECVD process makes three distinct depositions. First, a metal silicide forms by the reaction: MHal+Si+H2→MSix+HHal, where M represents a metal and Hal represents a preferred halogen or the like. Second, a metal nitride forms upon areas not containing Si by the reaction: MHal+N2+H2→MN+HHal. Third, a metal nitride forms upon areas of evolving metal silicide due to a diffusion barrier effect that makes formation of the metal silicide self limiting. Ultimately, a metal nitride layer will be uniformly disposed in a substantially uniform composition covering all underlying structures upon a semiconductor substrate. The inventive method can be used to form a semiconductor structure having a semiconductive substrate with an electrically active region therein, where a structure projects from the semiconductive substrate adjacent to the electrically active region. A first metal silicide is upon the electrically active region and a second metal silicide is upon the structure. A metal nitride layer extends continuously from the first metal silicide to the second metal silicide. An electrically conductive metallization material is upon the metal nitride layer.

    Abstract translation: 本发明涉及包括金属氮化物和金属硅化物的半导体结构，其中在作为结的一部分的有源区上形成金属硅化物层，以便于由需要较小器件所要求和规定的进一步小型化。 单个PECVD过程产生三个不同的沉积。 首先，通过以下反应形成金属硅化物：MHal + Si + H 2→MS xix + HHal，其中M表示金属，Hal表示优选的卤素等。 第二，通过反应在不含Si的区域形成金属氮化物：MHal + N2 + H2-> MN + HHal。 第三，由于扩散阻挡效应使得金属硅化物的形成在金属硅化物的区域上形成金属氮化物，从而形成金属硅化物自限制。 最终，金属氮化物层将被均匀地布置成覆盖半导体衬底上的所有下面的结构的基本均匀的组成。 本发明的方法可用于形成具有其中具有电活性区域的半导体衬底的半导体结构，其中结构从邻近电活性区域的半导体衬底突出。 第一金属硅化物在电活性区上，第二金属硅化物在该结构上。 金属氮化物层从第一金属硅化物连续延伸到第二金属硅化物。 导电金属化材料在金属氮化物层上。

    Semiconductor processing methods, methods of forming silicon dioxide methods of forming trench isolation regions, and methods of forming interlevel dielectric layers
    53.
    发明授权
    Semiconductor processing methods, methods of forming silicon dioxide methods of forming trench isolation regions, and methods of forming interlevel dielectric layers 失效
    半导体处理方法，形成二氧化硅的方法形成沟槽隔离区域的方法以及形成层间电介质层的方法

    公开(公告)号：US06323101B1

    公开(公告)日：2001-11-27

    申请号：US09146843

    申请日：1998-09-03

    Applicant: Weimin Li ,  Trung Tri Doan ,  David L. Chapek

    Inventor： Weimin Li ,  Trung Tri Doan ,  David L. Chapek

    IPC: H01L2176

    CPC classification number: H01L21/02164 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02337 ,  H01L21/3105 ,  H01L21/31612 ,  H01L21/76224

    Abstract: In one aspect, the invention includes a semiconductor processing method of removing water from a material comprising silicon, oxygen and hydrogen, the method comprising maintaining the material at a temperature of at least about 100° C., more preferably at least 300° C., and at a pressure of greater than 1 atmosphere to drive water from the material. In another aspect, the invention includes a semiconductor processing method of forming SiO2 having a wet etch removal rate of less than about 700 Angstroms/minute comprising: a) forming a layer comprising Si(OH)x; b) maintaining the Si(OH)x at a temperature of at least about 300° C. and at a pressure of greater than 1 atmosphere to drive water from the Si(OH)x; and c) converting the Si(OH)x to SiO2, the SiO2 having a wet etch removal rate of less than about 700 Angstroms/minute under the conditions of a buffered oxide etch utilizing 20:1 H2O:HF, at about atmospheric pressure and at a temperature of about 30° C. In another aspect, the invention includes a method of forming a trench isolation region comprising: a) forming a trench within a substrate; b) forming a layer comprising Si(OH)x within the trench and over the substrate; c) driving water from the layer comprising Si(OH)x at a pressure of greater than 1 atmosphere; d) converting the Si(OH)x to SiO2; and e) removing at least a portion of the SiO2.

    Abstract translation: 一方面，本发明包括从包括硅，氧和氢的材料中去除水的半导体加工方法，该方法包括将材料保持在至少约100℃，更优选至少300℃的温度。 ，并且在大于1个大气压的压力下驱动来自材料的水。 在另一方面，本发明包括形成具有小于约700埃/分钟的湿蚀刻去除速率的SiO 2的半导体加工方法，包括：a）形成包含Si（OH）x的层; b）将Si（OH）x维持在至少约300℃的温度和大于1个大气压的压力下驱动来自Si（OH）x的水; 和c）在约大气压下在使用20:1 H 2 O:H HF的缓冲氧化物蚀刻的条件下，将Si（OH）x转化为SiO 2，SiO 2具有小于约700埃/分钟的湿蚀刻去除速率，以及 在另一方面，本发明包括形成沟槽隔离区域的方法，包括：a）在衬底内形成沟槽; b）在沟槽内和衬底上形成包含Si（OH）x的层; c）在大于1大气压的压力下从含Si（OH）x的层驱动水; d）将Si（OH）x转化为SiO 2; 和e）除去SiO 2的至少一部分。

    High Power Lithium Ion Battery and the Method to Form
    54.
    发明申请
    High Power Lithium Ion Battery and the Method to Form 审中-公开

    公开(公告)号：US20200227727A1

    公开(公告)日：2020-07-16

    申请号：US16517598

    申请日：2018-01-19

    Applicant: Weimin Li

    Inventor： Weimin Li

    IPC: H01M4/139 ,  H01M10/0525 ,  H01M4/04 ,  H01M4/36

    Abstract: A vertical ferroelectric NAND memory system and method of making is disclosed. The vertical ferroelectric NAND memory system may comprise a stack of horizontal layers and a vertical structure. The stack of horizontal layers may be formed on a semiconductor substrate. The stack of horizontal layers may comprise a plurality gate electrode layers alternating with a plurality of insulating layers. The gate electrode layer may comprise conductive lines alternate with insulating lines. The insulating lines may be formed of insulating materials. The conductive lines are formed of a metal comprising W. The vertical structure may extend vertically through the stack of horizontal layers. The vertical structure may comprise a ferroelectric oxide layer, a vertical channel structure. The vertical channel structure may be formed of a semiconductor material.

    SEQUENTIAL PULSE DEPOSITION
    57.
    发明申请
    SEQUENTIAL PULSE DEPOSITION 审中-公开
    顺序脉冲沉积

    公开(公告)号：US20110212628A1

    公开(公告)日：2011-09-01

    申请号：US13037113

    申请日：2011-02-28

    Applicant: Weimin Li

    Inventor： Weimin Li

    IPC: H01L21/30

    CPC classification number: C23C16/45527 ,  C23C16/4408 ,  C23C16/45523 ,  C23C16/52 ,  H01L21/28506

    Abstract: A method for growing films on substrates using sequentially pulsed precursors and reactants, system and devices for performing the method, semiconductor devices so produced, and machine readable media containing the method.

    Abstract translation: 使用顺序脉冲前体和反应物在衬底上生长膜的方法，用于执行该方法的系统和装置，如此制备的半导体器件以及包含该方法的机器可读介质。

    Methods of forming intermediate semiconductor device structures using spin-on, photopatternable, interlayer dielectric materials
    59.
    发明授权
    Methods of forming intermediate semiconductor device structures using spin-on, photopatternable, interlayer dielectric materials 有权
    使用旋涂，光图案化，层间介电材料形成中间半导体器件结构的方法

    公开(公告)号：US07855154B2

    公开(公告)日：2010-12-21

    申请号：US11391774

    申请日：2006-03-29

    Applicant: Weimin Li ,  Gurtej S. Sandhu

    Inventor： Weimin Li ,  Gurtej S. Sandhu

    IPC: H01L21/316

    CPC classification number: G03F7/095 ,  G03F7/0757 ,  H01L21/02134 ,  H01L21/02137 ,  H01L21/02216 ,  H01L21/02222 ,  H01L21/02282 ,  H01L21/02348 ,  H01L21/311 ,  Y10T428/31663

    Abstract: A cap layer that enables a photopatternable, spin-on material to be used in the formation of semiconductor device structures at wavelengths that were previously unusable. The photopatternable, spin-on material is applied as a layer to a semiconductor substrate. The cap layer and a photoresist layer are each formed over the photopatternable layer. The cap layer absorbs or reflects radiation and protects the photopatternable layer from a first wavelength of radiation used in patterning the photoresist layer. The photopatternable, spin-on material is convertible to a silicon dioxide-based material upon exposure to a second wavelength of radiation.

    Abstract translation: 能够使光可图案化的旋涂材料用于以前不可用的波长形成半导体器件结构的盖层。 将可光刻图案的旋涂材料作为层施加到半导体衬底。 覆盖层和光致抗蚀剂层各自形成在光图案化层上。 盖层吸收或反射辐射，并保护光致图案层免受用于图案化光致抗蚀剂层的第一波长的辐射。 照射图案化的旋涂材料在暴露于第二波长辐射时可转换为二氧化硅基材料。

    Filled trench isolation structure
    60.
    发明授权
    Filled trench isolation structure 有权
    填充沟槽隔离结构

    公开(公告)号：US07550816B2

    公开(公告)日：2009-06-23

    申请号：US10866290

    申请日：2004-06-11

    Applicant: Li Li ,  Weimin Li ,  Gurtej S. Sandhu

    Inventor： Li Li ,  Weimin Li ,  Gurtej S. Sandhu

    IPC: H01L29/00

    CPC classification number: C23C16/4408 ,  C23C16/045 ,  C23C16/402 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31612 ,  H01L21/76224

    Abstract: A method for depositing a dielectric in a trench on a semiconductor substrate is provided. The dielectric is deposited by using an HDP-CVD system and performing a deposition of first and second layers of dielectric material. A first inert gas is utilized during the deposition of the first layer, and a second inert gas is utilized during the deposition of the second layer. Generally, a purge step is performed between the deposition of the first and second layers. The resulting dielectric layers are substantially free of voids and have low particle counts. Structures utilizing the filled trenches are also disclosed.

    Abstract translation: 提供了一种在半导体衬底上的沟槽中沉积电介质的方法。 通过使用HDP-CVD系统沉积电介质并执行介电材料的第一和第二层的沉积。 在第一层的沉积期间使用第一惰性气体，并且在沉积第二层期间使用第二惰性气体。 通常，在第一和第二层的沉积之间进行清洗步骤。 所得到的电介质层基本上没有空隙并且具有低的颗粒计数。 还公开了利用填充沟槽的结构。

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