公开(公告)号：US20240420796A1

公开(公告)日：2024-12-19

申请号：US18739969

申请日：2024-06-11

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. ALAM ,  Jacob T. WILLIAMS ,  Michael A. SADD ,  Kerry Joseph NAGEL ,  Sumio IKEGAWA ,  Frederick B. MANCOFF ,  Sanjeev AGGARWAL

IPC: G11C29/00 ,  G11C29/30 ,  G11C29/32

Abstract: A memory device including a first configuration bit group including a plurality of bits, the plurality of bits including: a plurality of configuration bits; at least one redundant configuration bit; a plurality of configuration bit multiplexers each configured to receive (i) a first input from a first bit in the plurality of bits and/or a second input from a second bit in the plurality of bits and (ii) a third input from a decoder, each of the first, second, and third inputs indicating a respective logical state, wherein the logical state includes a first state or a second state; and wherein, based on the logical state of the third input received from the decoder, each configuration bit multiplexer is configured to output: the logical state of the first input from the first bit, or the logical state of the second input from the second bit.

公开(公告)号：US20240306513A1

公开(公告)日：2024-09-12

申请号：US18664928

申请日：2024-05-15

Applicant: Everspin Technologies, Inc.

Inventor： Sanjeev AGGARWAL ,  Sarin DESHPANDE ,  Kerry NAGLE ,  Santosh KARRE

IPC: H10N50/01 ,  H01F10/32 ,  H10B61/00 ,  H10N50/80

CPC classification number: H10N50/01 ,  H10N50/80 ,  H01F10/3254 ,  H01F10/3272 ,  H10B61/00

Abstract: A magnetoresistive element may include a via providing an electrical connection between one or more metal regions and magnetoresistive devices. The via may include a transition metal layer, a tantalum-rich layer, and/or a cap layer. The transition metal layer may be formed by atomic layer deposition. Additionally, one or more layers of the via may be formed in the trench etched in one or more interlevel dielectric layers. The via may have an aspect ratio less than or equal to 2. The via may have a diameter less than or equal than a diameter of the magnetoresistive device electrically connected to one or more metal regions by the via.

公开(公告)号：US20230309416A1

公开(公告)日：2023-09-28

申请号：US18123729

申请日：2023-03-20

Applicant: Everspin Technologies, Inc.

Inventor： Sumio IKEGAWA ,  Han Kyu Lee ,  Sanjeev AGGARWAL ,  Jijun SUN ,  Syed M. ALAM ,  Tom ANDRE

IPC: H10N52/80 ,  H10B61/00 ,  H10N50/85 ,  H10N52/00 ,  H10N52/01

CPC classification number: H10N52/80 ,  H10B61/22 ,  H10N50/85 ,  H10N52/00 ,  H10N52/01

Abstract: The present disclosure is drawn to, among other things, a magnetoresistive device and a magnetoresistive memory comprising a plurality of such magnetoresistive devices. In some aspects, a magnetoresistive device may include a magnetically fixed region, a magnetically free region above or below the magnetically fixed region, and an intermediate region positioned between the magnetically fixed region and the magnetically free region, wherein the intermediate region includes a first dielectric material. The magnetoresistive device may also include encapsulation layers formed on opposing side walls of the magnetically free region, wherein the encapsulation layers include the first dielectric material.

公开(公告)号：US20230100514A1

公开(公告)日：2023-03-30

申请号：US18045539

申请日：2022-10-11

Applicant: Everspin Technologies, Inc.

Inventor： Kerry Joseph NAGEL ,  Sanjeev AGGARWAL ,  Thomas ANDRE ,  Sarin A. DESHPANDE

IPC: H01L27/22 ,  H01L43/08 ,  G11C11/16 ,  H01L43/12 ,  H01L43/02

Abstract: Magnetoresistive device architectures and methods for manufacturing are presented that facilitate integration of process steps associated with forming such devices into standard process flows used for surrounding logic/circuitry. In some embodiments, the magnetoresistive device structures are designed such that the devices are able to fit within the vertical dimensions of the integrated circuit associated with a single metal layer and a single layer of interlayer dielectric material. Integrating the processing for the magnetoresistive devices can include using the same standard interlayer dielectric material as used in the surrounding circuits on the integrated circuit as well as using standard vias to interconnect to at least one of the electrodes of the magnetoresistive devices.

公开(公告)号：US20230053632A1

公开(公告)日：2023-02-23

申请号：US18045504

申请日：2022-10-11

Applicant: Everspin Technologies, Inc.

Inventor： Sanjeev AGGARWAL ,  SHIMON ,  Kerry Joseph NAGEL

IPC: H01L43/14 ,  H01L27/22 ,  H01L43/04 ,  H01L43/06

Abstract: A method of manufacturing a magnetoresistive device may comprise forming a first magnetic region, an intermediate region, and a second magnetic region of a magnetoresistive stack above a via; removing at least a portion of the second magnetic region using a first etch; removing at least a portion of the intermediate region and at least a portion of the first magnetic region using a second etch; removing at least a portion of material redeposited on the magnetoresistive stack using a third etch; and rendering at least a portion of the redeposited material remaining on the magnetoresistive stack electrically non-conductive.

公开(公告)号：US20230026294A1

公开(公告)日：2023-01-26

申请号：US17652905

申请日：2022-02-28

Applicant: Everspin Technologies, Inc.

Inventor： Dimitri HOUSSAMEDDINE ,  Syed M. ALAM ,  Sanjeev AGGARWAL

IPC: H03K19/1776 ,  G11C11/16 ,  G11C13/00 ,  H03K19/17724 ,  H03K19/17784

Abstract: The present disclosure is drawn to, among other things, a configuration bit including at least four resistive elements and a voltage amplifier. At least two first resistive elements may be electrically connected in series via a first electrode and at least two second resistive elements may be electrically connected in series via a second electrode. The at least two first resistive elements may be electrically connected in parallel to the at least two second resistive elements via a third electrode and a fourth electrode. The first electrode and the second electrode may be electrically connected to a voltage supply. The third electrode and the fourth electrode may be electrically connected to an input of the voltage amplifier.

公开(公告)号：US20220209104A1

公开(公告)日：2022-06-30

申请号：US17134683

申请日：2020-12-28

Applicant: Everspin Technologies, Inc.

Inventor： Sanjeev AGGARWAL ,  SHIMON ,  Kerry Joseph NAGEL

IPC: H01L43/14 ,  H01L27/22 ,  H01L43/04 ,  H01L43/06

Abstract: A method of manufacturing a magnetoresistive device may comprise forming a first magnetic region, an intermediate region, and a second magnetic region of a magnetoresistive stack above a via; removing at least a portion of the second magnetic region using a first etch; removing at least a portion of the intermediate region and at least a portion of the first magnetic region using a second etch; removing at least a portion of material redeposited on the magnetoresistive stack using a third etch; and rendering at least a portion of the redeposited material remaining on the magnetoresistive stack electrically non-conductive.

公开(公告)号：US20200075843A1

公开(公告)日：2020-03-05

申请号：US16561418

申请日：2019-09-05

Applicant: Everspin Technologies, Inc.

Inventor： Kerry NAGEL ,  Sanjeev AGGARWAL

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

Abstract: A magnetoresistive device may include a first plurality of magnetic tunnel junction (MTJ) bits arranged in a first XY plane, and a second plurality of MTJ bits arranged in a second XY plane that is spaced apart from the first XY plane in a Z direction. And, the MTJ bits of the first plurality of MTJ bits may be spaced apart from the MTJ bits of the second plurality of MTJ bits in the X and Y directions.

公开(公告)号：US20200043979A1

公开(公告)日：2020-02-06

申请号：US16601848

申请日：2019-10-15

Applicant: Everspin Technologies, Inc.

Inventor： Jijun SUN ,  Sanjeev AGGARWAL ,  Han-Jong CHIA ,  Jon M. SLAUGHTER ,  Renu WHIG

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  G11C11/16 ,  H01L43/12 ,  G11B5/39 ,  H01L43/10

Abstract: A magnetoresistive stack/structure and method of manufacturing same comprising wherein the stack/structure includes a seed region, a fixed magnetic region disposed on and in contact with the seed region, a dielectric layer(s) disposed on the fixed magnetic region and a free magnetic region disposed on the dielectric layer(s). In one embodiment, the seed region comprises an alloy including nickel and chromium having (i) a thickness greater than or equal to 40 Angstroms (+/−10%) and less than or equal to 60 Angstroms (+/−10%), and (ii) a material composition or content of chromium within a range of 25-60 atomic percent (+/−10%) or 30-50 atomic percent (+/−10%).

公开(公告)号：US20190280045A1

公开(公告)日：2019-09-12

申请号：US16293729

申请日：2019-03-06

Applicant: Everspin Technologies, Inc.

Inventor： Sanjeev AGGARWAL ,  Kevin Conley ,  Sarin A. Deshpande

IPC: H01L27/22 ,  H01L43/02 ,  G11C11/16

Abstract: A magnetoresistive device may include an annular-shaped magnetic tunnel junction (MTJ) bit having an inner end and an outer end. The MTJ bit may include an annular-shaped magnetically free region and an annular-shaped magnetically fixed region separated by an annular-shaped intermediate layer. A first electrical conductor may be in electrical contact with the inner end of the MTJ bit, and a second electrical conductor may be in electrical contact with the outer end of the MTJ bit.