公开(公告)号：US09443956B2

公开(公告)日：2016-09-13

申请号：US14675880

申请日：2015-04-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong Yu ,  Biao Zuo ,  Jin Ping Liu ,  Huang Liu

IPC: H01L29/66

CPC classification number: H01L29/6656 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method includes forming a line feature above a substrate. Carbon-containing spacers are formed on sidewalls of the line feature. A first dielectric layer is formed above the carbon spacers and the line feature. The first dielectric layer is planarized to expose upper ends of the carbon-containing spacers. An ashing process is performed to remove the carbon-containing spacers and define air gaps adjacent the line feature. A cap layer is formed to seal the upper ends of the air gaps.

Abstract translation: 一种方法包括在衬底上形成线特征。 含碳隔离物形成在线特征的侧壁上。 第一电介质层形成在碳间隔物和线特征之上。 平面化第一介电层以暴露含碳间隔物的上端。 执行灰化处理以除去含碳间隔物并限定与线特征相邻的气隙。 形成盖层以密封气隙的上端。

公开(公告)号：US20160163816A1

公开(公告)日：2016-06-09

申请号：US14675880

申请日：2015-04-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong Yu ,  Biao Zuo ,  Jin Ping Liu ,  Huang Liu

IPC: H01L29/66

CPC classification number: H01L29/6656 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method includes forming a line feature above a substrate. Carbon-containing spacers are formed on sidewalls of the line feature. A first dielectric layer is formed above the carbon spacers and the line feature. The first dielectric layer is planarized to expose upper ends of the carbon-containing spacers. An ashing process is performed to remove the carbon-containing spacers and define air gaps adjacent the line feature. A cap layer is formed to seal the upper ends of the air gaps.

Abstract translation: 一种方法包括在衬底上形成线特征。 含碳隔离物形成在线特征的侧壁上。 第一电介质层形成在碳间隔物和线特征之上。 平面化第一介电层以暴露含碳间隔物的上端。 执行灰化处理以除去含碳间隔物并限定与线特征相邻的气隙。 形成盖层以密封气隙的上端。

公开(公告)号：US09230822B1

公开(公告)日：2016-01-05

申请号：US14306920

申请日：2014-06-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong Yu ,  Haigou Huang ,  Jin Ping Liu ,  Huang Liu

IPC: H01L21/3105 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L21/31055 ,  H01L21/02318 ,  H01L21/02326 ,  H01L21/0234 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/823821 ,  H01L21/823842

Abstract: A semiconductor structure with mixed n-type and p-type non-planar transistors includes a residual overlapping mask bump on one or more of the dummy gates. A dielectric layer is created over the structure having a top surface above the residual bump, for example, using a blanket deposition and chemical-mechanical underpolish (i.e., stopping before exposing the gate cap). The residual bump is then transformed into a same material as the dielectric, either in its entirety and then removing the combined dielectric, or by removing the dielectric first and partly removing the residual bump, the remainder of which is then transformed and the dielectric removed. In either case, the structure is planarized for further processing.

Abstract translation: 具有混合n型和p型非平面晶体管的半导体结构包括在一个或多个虚拟栅极上的残留重叠掩模凸块。 例如，使用覆盖沉积和化学机械的低估（即，在暴露栅极盖之前停止），在该结构上方形成介电层，该顶表面具有顶部表面。 然后将剩余的凸块转变成与电介质完全相同的材料，然后去除组合的电介质，或者通过首先去除电介质并部分去除残余凸块，然后将其余部分转化并除去电介质。 在任一种情况下，将结构平坦化用于进一步处理。

公开(公告)号：US09153693B2

公开(公告)日：2015-10-06

申请号：US13917019

申请日：2013-06-13

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Hong Yu ,  Wang Zheng ,  Huang Liu ,  Yongsik Moon

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/28 ,  H01L29/49

CPC classification number: H01L29/785 ,  H01L21/28008 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/66795

Abstract: An intermediate semiconductor structure of a FinFET device in fabrication includes a substrate, a plurality of fin structures coupled to the substrate and a dummy gate disposed perpendicularly over the fin structures. A portion of the dummy gate is removed between the fin structures to create one or more vias and the one or more vias are filled with a dielectric. The dummy gate is then replaced with a metal gate formed around the dielectric-filled vias.

Abstract translation: 在制造中的FinFET器件的中间半导体结构包括衬底，耦合到衬底的多个翅片结构和垂直于翅片结构设置的虚拟栅极。 在翅片结构之间去除虚拟栅极的一部分以产生一个或多个通孔，并且一个或多个通孔用电介质填充。 然后用在电介质填充的通孔周围形成的金属栅极替换虚拟栅极。

公开(公告)号：US10784342B1

公开(公告)日：2020-09-22

申请号：US16385197

申请日：2019-04-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Hong ,  Hong Yu ,  Jianwei Peng ,  Hui Zhan

IPC: H01L29/06 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/762 ,  H01L29/66

Abstract: Structures that include a single diffusion break and methods of forming a single diffusion break. A source/drain region is arranged inside a first cavity in a semiconductor fin, and a dielectric layer is arranged inside a second cavity in the semiconductor fin. A liner, which is composed of a dielectric material, includes a section that is arranged inside the second cavity laterally between the dielectric layer and the source/drain region.

公开(公告)号：US20200286790A1

公开(公告)日：2020-09-10

申请号：US16296469

申请日：2019-03-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Hong ,  Hong Yu ,  Tao Chu ,  Bingwu Liu

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L21/308

Abstract: One illustrative method disclosed herein includes forming a conformal SMCM layer above a conformal high-k gate insulation layer within each of first and second replacement gate cavities (RGC), removing the SMCM layer from the first RGC while leaving the SMCM layer in position within the second RGC, forming a first conformal metal-containing material (MCM) layer above the gate insulation layer within the first RGC and above the SMCM layer in position within the second RGC, removing the first conformal MCM layer and the conformal SMCM layer positioned within the second RGC while leaving the first conformal MCM layer within the first RGC, and forming a second conformal MCM layer above the first conformal MCM layer positioned within the first RGC and above the gate insulation layer positioned within the second RGC.

公开(公告)号：US10074732B1

公开(公告)日：2018-09-11

申请号：US15622902

申请日：2017-06-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xinyuan Dou ,  Hui Zang ,  Hong Yu ,  Yanzhen Wang

IPC: H01L29/00 ,  H01L21/8228 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L29/66818 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/785

Abstract: One illustrative method disclosed herein includes, among other things, forming first and second fins for a short channel FinFET device (“SCD”) and a long channel FinFET device (“LCD”), performing an oxidation process to form a sacrificial oxide material selectively on the channel portion of one of the first and second fins but not on the channel portion of the other of the first and second fins, removing the sacrificial oxide material from the fin on which it is formed so as to produce a reduced-size channel portion on that fin that is less than the initial size of the channel portion of the other non-oxidized fin, and forming first and second gate structures for the SCD and LCD devices.

公开(公告)号：US09935104B1

公开(公告)日：2018-04-03

申请号：US15589292

申请日：2017-05-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haiting Wang ,  Wei Zhao ,  Hong Yu ,  Xusheng Wu ,  Hui Zang ,  Zhenyu Hu

IPC: H01L21/84 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/311 ,  H01L29/06 ,  H01L21/308 ,  H01L21/02

CPC classification number: H01L27/0886 ,  H01L21/02164 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/762 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/0649

Abstract: Disclosed is a semiconductor structure, including at least one fin-type field effect transistor and at least one single-diffusion break (SDB) type isolation region, and a method of forming the semiconductor structure. In the method, an isolation bump is formed above an isolation region within a semiconductor fin and sidewall spacers are formed on the bump. During an etch process to reduce the height of the bump and to remove isolation material from the sidewalls of the fin, the sidewall spacers prevent lateral etching of the bump. During an etch process to form source/drain recesses in the fin, the sidewalls spacers protect the semiconductor material adjacent to the isolation region. Consequently, the sides and bottom of each recess include semiconductor surfaces and the angle of the top surfaces of the epitaxial source/drain regions formed therein is minimized, thereby minimizing the risk of unlanded source/drain contacts.

公开(公告)号：US20160190130A1

公开(公告)日：2016-06-30

申请号：US14676165

申请日：2015-04-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong Yu ,  HongLiang Shen ,  Zhenyu Hu ,  Jin Ping Liu

IPC: H01L27/088 ,  H01L21/762 ,  H01L21/306 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/28 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/3105

CPC classification number: H01L27/0886 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/7851

Abstract: A method includes forming a fin in a semiconductor substrate. A plurality of sacrificial gate structures are formed above the fin. A selected one of the sacrificial gate structures is removed to define a first opening that exposes a portion of the fin. An etch process is performed through the first opening on the exposed portion of the fin to define a first recess in the fin. The first recess is filled with a dielectric material to define a diffusion break in the fin. A device includes a fin defined in a substrate, a plurality of gates formed above the fin, a plurality of recesses filled with epitaxial material defined in the fin, and a diffusion break defined at least partially in the fin between two of the recesses filled with epitaxial material and extending above the fin.

Abstract translation: 一种方法包括在半导体衬底中形成翅片。 在翅片上形成多个牺牲栅极结构。 去除所选择的牺牲栅极结构之一以限定暴露鳍片的一部分的第一开口。 通过翅片的暴露部分上的第一开口进行蚀刻处理，以限定翅片中的第一凹部。 第一凹部填充有电介质材料以限定散热片中的扩散断裂。 一种装置包括限定在衬底中的翅片，形成在鳍片上方的多个栅极，填充有限定在翅片中的外延材料的多个凹槽以及至少部分地限定在翅片中的两个凹陷之间的扩散断裂， 外延材料并在翅片上方延伸。

公开(公告)号：US20160163830A1

公开(公告)日：2016-06-09

申请号：US14560035

申请日：2014-12-04

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Hong Yu ,  Jin Ping Liu ,  Haigou Huang ,  Huang Liu

IPC: H01L29/66 ,  H01L21/3105 ,  H01L21/02

CPC classification number: H01L29/66795 ,  H01L21/02326 ,  H01L21/31053 ,  H01L21/31111 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636

Abstract: A method includes forming at least one fin in a semiconductor substrate. A placeholder gate structure is formed above the fin. The placeholder gate structure includes a placeholder material and a cap structure defined on a top surface of the placeholder material. The cap structure includes a first cap layer disposed above the placeholder material and a second cap layer disposed above the first cap layer. An oxidization process is performed on at least a portion of the second cap layer to form an oxidized region above a remaining portion of the second cap layer. A portion of the oxidized region is removed to expose the remaining portion. The remaining portion of the second cap layer is removed. The first cap layer is removed to expose the placeholder material. The placeholder material is replaced with a conductive material.

Abstract translation: 一种方法包括在半导体衬底中形成至少一个翅片。 在翅片上形成占位符门结构。 占位符门结构包括在占位符材料的顶表面上限定的占位符材料和盖结构。 盖结构包括设置在占位符材料上方的第一盖层和设置在第一盖层上方的第二盖层。 在第二盖层的至少一部分上进行氧化处理，以在第二盖层的剩余部分上方形成氧化区域。 去除氧化区域的一部分以露出剩余部分。 去除第二盖层的剩余部分。 移除第一盖层以露出占位符材料。 占位符材料被导电材料代替。