公开(公告)号：US20170301544A1

公开(公告)日：2017-10-19

申请号：US15097861

申请日：2016-04-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min-hwa CHI ,  Meixiong ZHAO ,  Kuniko KIKUTA

IPC: H01L21/28 ,  H01L29/66 ,  H01L29/40 ,  H01L21/02 ,  H01L29/08 ,  H01L29/49

CPC classification number: H01L21/28088 ,  H01L21/02656 ,  H01L21/265 ,  H01L21/28114 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method of making a transistor for an integrated circuit includes providing a substrate and forming a dummy gate for the transistor within a gate trench on the substrate. The gate trench includes sidewalls, a trench bottom, and a trench centerline extending normally from a center portion of the trench bottom. The dummy gate is removed from the gate trench. A gate dielectric layer is disposed within the gate trench. A gate work-function metal layer is disposed over the gate dielectric layer, the work-function metal layer including a pair of corner regions proximate the trench bottom. An angled implantation process is utilized to implant a work-function tuning species into the corner regions at a tilt angle relative to the trench centerline, the tilt angle being greater than zero.

公开(公告)号：US20170294336A1

公开(公告)日：2017-10-12

申请号：US15634091

申请日：2017-06-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Min-hwa CHI

IPC: H01L21/74 ,  H01L29/06 ,  H01L29/10 ,  H01L21/762

CPC classification number: H01L21/743 ,  H01L21/76229 ,  H01L21/7624 ,  H01L21/76283 ,  H01L21/76831 ,  H01L21/76877 ,  H01L23/481 ,  H01L29/0649 ,  H01L29/1087

Abstract: Devices and methods of fabricating integrated circuit devices for dynamically applying bias to back plates and/or p-well regions are provided. One method includes, for instance: obtaining a wafer with a silicon substrate, at least one first oxide layer, at least one silicon layer, and at least one second oxide layer; forming at least one recess in the wafer; depositing at least one third oxide layer over the wafer and filling the at least one recess; depositing a silicon nitride layer over the wafer; and forming at least one opening having sidewalls and a bottom surface within the filled at least one recess. An intermediate semiconductor device is also disclosed.

公开(公告)号：US20170294309A1

公开(公告)日：2017-10-12

申请号：US15093310

申请日：2016-04-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Min-hwa CHI

IPC: H01L21/033 ,  H01L21/02 ,  H01L21/311 ,  H01L21/8234

CPC classification number: H01L21/0337 ,  H01L21/3086 ,  H01L21/32139 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823456

Abstract: A method includes, for example, providing a starting semiconductor structure having a plurality of material lines disposed over a hard mask, and the hard mask disposed over a patternable layer, forming a protective layer over a portion of at least one material line, the at least one protected material line and at least one unprotected material line having a same critical dimension, oxidizing the at least one unprotected material line to increase the critical dimension compared to the first critical dimension of the at least one protected material line, and etching at least a portion of the oxidized unprotected material line so that the etched critical dimension of the at least one etched material line is different from the first critical dimension of the at least one protected material line.

公开(公告)号：US20170294308A1

公开(公告)日：2017-10-12

申请号：US15093292

申请日：2016-04-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Min-hwa CHI

IPC: H01L21/033 ,  H01L21/02 ,  H01L21/311 ,  H01L21/8234

CPC classification number: H01L21/0337 ,  H01L21/02238 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823475

Abstract: A method includes, for example, a starting semiconductor structure comprising a plurality of material lines disposed over a hard mask, and the hard mask disposed over a patternable layer, forming a first protective layer over some of the plurality of material lines, the protected material lines and the unprotected material lines having a same corresponding first critical dimension, oxidizing the unprotected material lines so that the oxidized unprotected material lines have an increased second critical dimension greater than the first critical dimension, removing the first protective layer, forming a second protective layer over some of the plurality of protected material lines having the first critical dimension and some of the oxidized material lines having the second critical dimension, and oxidizing the unprotected material lines so that the oxidized unprotected material lines have an increased third critical dimension greater than the first critical dimension.

公开(公告)号：US20170207216A1

公开(公告)日：2017-07-20

申请号：US15001903

申请日：2016-01-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wen Pin PENG ,  Min-hwa CHI

IPC: H01L27/088 ,  H01L21/306 ,  H01L29/06 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/30604 ,  H01L21/823412 ,  H01L21/823431 ,  H01L29/0657

Abstract: A multi-Vt FinFET includes a semiconductor substrate, multiple first fins coupled to the semiconductor substrate having a first fin pitch, and multiple second fins coupled to the semiconductor substrate having a second fin pitch larger than the first fin pitch. The semiconductor structure further includes transistor(s) on the multiple first fins, and transistor(s) on the multiple second fins, a threshold voltage of the transistor(s) on the multiple second fins being higher than that of the transistor(s) on the multiple first fins.

公开(公告)号：US20170200786A1

公开(公告)日：2017-07-13

申请号：US14993543

申请日：2016-01-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Min-hwa CHI

IPC: H01L29/06 ,  H01L27/11 ,  H01L21/308 ,  H01L27/12 ,  H01L21/84 ,  H01L21/3065

CPC classification number: H01L29/0692 ,  H01L21/3086 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/1104 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785

Abstract: Shaped mandrels are used to form closed-loop spacer(s) around the shaped mandrels, after which the shaped mandrels are removed, leaving a closed-loop fin. A transistor includes U-shaped portion(s) of a closed-loop fin, and a gate across channel region(s) of the U-shaped portion(s) of a closed-loop fin. A semiconductor structure includes portion(s) of closed-loop fin(s), and transistors formed from the portion(s) of closed-loop fin(s).

公开(公告)号：US20170062442A1

公开(公告)日：2017-03-02

申请号：US14842345

申请日：2015-09-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Suraj K. PATIL ,  Ajey P. JACOB ,  Min-hwa CHI

IPC: H01L27/112

CPC classification number: H01L27/11206 ,  G11C13/0002 ,  G11C13/0009 ,  G11C13/0069 ,  G11C13/025 ,  G11C2013/008 ,  H01L23/5256 ,  H01L23/53276 ,  H01L27/112 ,  H01L29/0676 ,  H01L29/413

Abstract: Methods and structures for programmable device fabrication are provided. The methods for fabricating a programmable device include, for example forming at least one via opening in a layer of the programmable device and providing a catalyzing material over a lower surface of the at least one via opening; forming a plurality of nanowires or nanotubes in the at least one via opening using the catalyzing material as a catalyst for the forming of the plurality of nanowires or nanotubes; and providing a dielectric material in the at least one via opening so that the dielectric material surrounds the plurality of nanowires or nanotubes. The programmable device may, in subsequent or separate programming steps, have programming of the programmable device made permanent via thermal oxidation of the dielectric material and the plurality of nanowires or nanotubes, leaving a non-conducting material behind in the at least one via opening.

Abstract translation: 提供了可编程器件制造的方法和结构。 制造可编程装置的方法包括例如在可编程装置的层中形成至少一个通孔，并在至少一个通孔开口的下表面上提供催化材料; 在所述至少一个通孔开口中使用所述催化材料形成多个纳米线或纳米管作为用于形成所述多个纳米线或纳米管的催化剂; 以及在所述至少一个通孔开口中提供介电材料，使得所述电介质材料包围所述多个纳米线或纳米管。 可编程设备在随后或单独的编程步骤中可以通过介电材料和多个纳米线或纳米管的热氧化使可编程器件的编程永久化，在至少一个通孔开口之后留下非导电材料。

公开(公告)号：US20160225852A1

公开(公告)日：2016-08-04

申请号：US14609504

申请日：2015-01-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shishir RAY ,  Bharat KRISHNAN ,  Min-hwa CHI

IPC: H01L29/08 ,  H01L21/268 ,  H01L21/324 ,  H01L29/04 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/268 ,  H01L21/3247 ,  H01L29/045 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7847 ,  H01L29/7848

Abstract: Methods are providing for fabricating transistors having at least one source region or drain region with a stressed portion. The methods include: forming, within a cavity of a substrate structure, the at least one source region or drain region with the internal stress; and resurfacing the at least one source region or drain region to reduce surface defects of the at least one source region or drain region without relaxing the stressed portion thereof. For instance, the resurfacing can include melting an upper portion of the at least one source region or drain region. In addition, the resurfacing can include re-crystallizing an upper portion of the at least one source region or drain region, and/or providing the at least one source region or drain region with at least one {111} surface.

Abstract translation: 提供制造具有至少一个具有应力部分的源极区或漏极区的晶体管的方法。 所述方法包括：在衬底结构的空腔内形成具有内部应力的至少一个源极区域或漏极区域; 以及重新铺展所述至少一个源极区域或漏极区域以减少所述至少一个源极区域或漏极区域的表面缺陷，而不放松其应力部分。 例如，表面重排可以包括熔化至少一个源区或漏区的上部。 另外，重新表面可以包括重新结晶至少一个源区或漏区的上部，和/或向至少一个源区或漏区提供至少一个{111}表面。

公开(公告)号：US20160225675A1

公开(公告)日：2016-08-04

申请号：US14611769

申请日：2015-02-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yan Ping SHEN ,  Min-hwa CHI ,  Xusheng WU ,  Weihua TONG ,  Haiting WANG

IPC: H01L21/8238 ,  H01L21/28 ,  H01L27/092 ,  H01L29/66 ,  H01L29/423 ,  H01L29/49 ,  H01L21/3215 ,  H01L21/285

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28568 ,  H01L21/3215 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/66545

Abstract: A method of forming RMG multi-WF layers for an nFET and pFET, and the resulting device are provided. Embodiments include forming a Si fin; forming a nFET RMG trench and a pFET RMG trench; forming a first Ti layer in the nFET and pFET RMG trenches; implanting N2 in the first Ti layer vertically at a 0° implant angle in the pFET RMG trench; annealing the N2 implanted first Ti layer to form a TiN layer in the pFET RMG trench; stripping un-reacted Ti of the first Ti layer; forming a second Ti layer in the nFET and pFET RMG trenches; implanting Al or C in the second Ti layer vertically at 0°; annealing the Al or C implanted second Ti layer to form TiAl or TiC at a bottom of the nFET and pFET RMG trenches, respectively; and filling the nFET and pFET RMG trenches with Al or W.

Abstract translation: 提供一种形成用于nFET和pFET的RMG多WF层的方法，以及所得到的器件。 实施例包括形成Si翅片; 形成nFET RMG沟槽和pFET RMG沟槽; 在nFET和pFET RMG沟槽中形成第一Ti层; 在pFET RMG沟槽中以0°注入角垂直注入第一Ti层中的N 2; 对N 2注入的第一Ti层退火以在pFET RMG沟槽中形成TiN层; 剥离第一Ti层的未反应的Ti; 在nFET和pFET RMG沟槽中形成第二Ti层; 在0°垂直方向将Al或C注入第二Ti层; 退火Al或C注入的第二Ti层，分别在nFET和pFET RMG沟槽的底部形成TiAl或TiC; 并用Al或W填充nFET和pFET RMG沟槽。

公开(公告)号：US20160126336A1

公开(公告)日：2016-05-05

申请号：US14527250

申请日：2014-10-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng WU ,  Changyong XIAO ,  Min-hwa CHI

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/423 ,  H01L21/311 ,  H01L29/417

CPC classification number: H01L29/66515 ,  H01L29/41775 ,  H01L29/42356 ,  H01L29/6653 ,  H01L29/66545

Abstract: Processes for forming merged CA/CB constructs and the resulting devices are disclosed. Embodiments include providing a replacement metal gate (RMG) between first and second sidewall spacers surrounded by an insulator on a substrate, the RMG having a dielectric layer directly on the first and second sidewall spacers and having metal on the dielectric layer; providing an oxide layer over the insulator, the first and second sidewall spacers, and the RMG; forming a source/drain contact hole through the oxide layer and the insulator, adjacent to the first sidewall spacer; forming a gate contact hole through the oxide layer over the source/drain contact hole and extending to the metal of the RMG; enlarging the source/drain contact hole to the metal of the RMG; and filling the enlarged source/drain contact hole and gate contact hole with metal.

Abstract translation: 公开了形成合并的CA / CB结构和所得到的设备的过程。 实施例包括在由衬底上的绝缘体围绕的第一和第二侧壁间隔之间提供置换金属栅极（RMG），RMG直接在第一和第二侧壁间隔物上并且在电介质层上具有金属; 在绝缘体上方提供氧化物层，第一和第二侧壁间隔物以及RMG; 形成与所述第一侧壁间隔物相邻的所述氧化物层和所述绝缘体的源极/漏极接触孔; 在源极/漏极接触孔上形成通过氧化物层的栅极接触孔并延伸到RMG的金属; 将源极/漏极接触孔扩大到RMG的金属; 并用金属填充放大的源极/漏极接触孔和栅极接触孔。