公开(公告)号：US20180138177A1

公开(公告)日：2018-05-17

申请号：US15352963

申请日：2016-11-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tek Po Rinus LEE ,  Bharat KRISHNAN ,  Jinping LIU ,  Hui ZANG ,  Judson Robert HOLT

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/3205 ,  H01L29/08 ,  H01L29/45 ,  H01L29/66

CPC classification number: H01L27/092 ,  H01L21/28525 ,  H01L21/76843 ,  H01L21/76858 ,  H01L21/76865 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/45 ,  H01L29/456

Abstract: Formation of band-edge contacts include, for example, providing an intermediate semiconductor structure comprising a substrate and a gate thereon and source/drain regions adjacent the gate, depositing a non-epitaxial layer on the source/drain regions, deposing a metal layer on the non-epitaxial layer, and forming metal alloy contacts from the deposited non-epitaxial layer and metal layer on the source/drain regions by annealing the deposited non-epitaxial layer and metal layer.

公开(公告)号：US20150035062A1

公开(公告)日：2015-02-05

申请号：US13954289

申请日：2013-07-30

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Jinping LIU ,  Bharat KRISHNAN ,  Bongki LEE ,  Vidmantas SARGUNAS ,  Weihua TONG ,  Seung KIM

IPC: H01L29/66 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L21/823821 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a channel region of a fin structure with a first side, a second side, an exposed first end surface and an exposed second end surface. A gate is formed overlying the first side and second side of the channel region. The method includes implanting ions into the channel region through the exposed first end surface and the exposed second end surface. Further, the method includes forming source/drain regions of the fin structure adjacent the exposed first end surface and the exposed second end surface of the channel region.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个实施例中，一种用于制造集成电路的方法包括：具有第一侧，第二侧，暴露的第一端面和暴露的第二端面的翅片结构的沟道区。 形成在沟道区域的第一侧和第二侧上方的栅极。 该方法包括通过暴露的第一端表面和暴露的第二端表面将离子注入沟道区域。 此外，所述方法包括在所述通道区域的暴露的第一端面和暴露的第二端面附近形成所述鳍结构的源极/漏极区域。

公开(公告)号：US20170200792A1

公开(公告)日：2017-07-13

申请号：US14993537

申请日：2016-01-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chang Ho MAENG ,  Andy WEI ,  Anthony OZZELLO ,  Bharat KRISHNAN ,  Guillaume BOUCHE ,  Haifeng SHENG ,  Haigou HUANG ,  Huang LIU ,  Huy M. CAO ,  Ja-Hyung HAN ,  SangWoo LIM ,  Kenneth A. BATES ,  Shyam PAL ,  Xintuo DAI ,  Jinping LIU

IPC: H01L29/40 ,  H01L21/02 ,  H01L21/28 ,  H01L29/423

CPC classification number: H01L29/401 ,  H01L21/02126 ,  H01L21/02282 ,  H01L21/28229 ,  H01L29/41791 ,  H01L29/4232 ,  H01L29/78

Abstract: Methods of MOL S/D contact patterning of RMG devices without gouging of the Rx area or replacement of the dielectric are provided. Embodiments include forming a SOG layer around a RMG structure, the RMG structure having a contact etch stop layer and a gate cap layer; forming a lithography stack over the SOG and gate cap layers; patterning first and second TS openings through the lithography stack down to the SOG layer; removing a portion of the SOG layer through the first and second TS openings, the removing selective to the contact etch stop layer; converting the SOG layer to a SiO2 layer; forming a metal layer over the SiO2 layer; and planarizing the metal and SiO2 layers down to the gate cap layer.

公开(公告)号：US20160005657A1

公开(公告)日：2016-01-07

申请号：US14853537

申请日：2015-09-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bharat KRISHNAN ,  Jody A. FRONHEISER ,  Jinping LIU ,  Bongki LEE

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/324

CPC classification number: H01L21/823431 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/02587 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/324 ,  H01L29/0657 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor structure includes a bulk silicon substrate and one or more silicon fins coupled to the bulk silicon substrate. Stress-inducing material(s), such as silicon, are epitaxially grown on the fins into naturally diamond-shaped structures using a controlled selective epitaxial growth. The diamond shaped structures are subjected to annealing at about 750° C. to about 850° C. to increase an area of (100) surface orientation by reshaping the shaped structures from the annealing. Additional epitaxial material is grown on the increased (100) area. Multiple cycles of increasing the area of (100) surface orientation (e.g., by the annealing) and growing additional epitaxial material on the increased area are performed to decrease the width of the shaped structures, increasing the space between them to prevent them from merging, while also increasing their volume.

Abstract translation: 半导体结构包括体硅衬底和耦合到体硅衬底的一个或多个硅散热片。 使用受控的选择性外延生长，诸如硅的应力诱导材料在翅片上外延生长成天然的菱形结构。 金刚石结构在约750℃至约850℃下进行退火，以通过从退火中重塑成形结构来增加（100）表面取向的面积。 额外的外延材料在增加的（100）区域上生长。 进行增加（100）表面取向（例如通过退火）的面积和在增加的面积上生长另外的外延材料的多个循环以减小成形结构的宽度，增加它们之间的空间以防止它们的合并， 同时也增加了他们的数量。

公开(公告)号：US20150194307A1

公开(公告)日：2015-07-09

申请号：US14147666

申请日：2014-01-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Churamani GAIRE ,  Bharat KRISHNAN ,  Jin Ping LIU

IPC: H01L21/02 ,  H01L27/092 ,  H01L29/10

CPC classification number: H01L27/0924 ,  H01L21/823821 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7851

Abstract: Methods for fabricating a strained fin structure are provided which include: providing a virtual substrate material over a substrate structure, the virtual substrate material having a virtual substrate lattice constant and a virtual substrate lattice structure; providing a first material over a region of the virtual substrate material, the first material acquiring a strained first material lattice structure by, in part, conforming to the virtual substrate lattice structure; and etching a first fin pattern into the first material. The method may include providing a second material over a second region of the virtual substrate material, the second material acquiring a strained lattice structure by, in part, conforming to the virtual substrate lattice structure, and etching a fin pattern into the second material. The resultant device may have tensile strained fin structures or compressively strained fin structures, or both.

Abstract translation: 提供了制造应变翅片结构的方法，其包括：在衬底结构上提供虚拟衬底材料，虚拟衬底材料具有虚拟衬底晶格常数和虚拟衬底晶格结构; 在所述虚拟衬底材料的区域上提供第一材料，所述第一材料部分地通过符合所述虚拟衬底晶格结构获得应变的第一材料晶格结构; 并将第一鳍图案蚀刻到第一材料中。 该方法可以包括在虚拟衬底材料的第二区域上提供第二材料，第二材料部分地通过符合虚拟衬底晶格结构并且将鳍状图案蚀刻到第二材料中来获得应变晶格结构。 所得到的装置可以具有拉伸应变翅片结构或压缩应变翅片结构，或两者。

公开(公告)号：US20200066593A1

公开(公告)日：2020-02-27

申请号：US16109258

申请日：2018-08-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tek Po Rinus LEE ,  Annie LEVESQUE ,  Qun GAO ,  Hui ZANG ,  Rishikesh KRISHNAN ,  Bharat KRISHNAN ,  Curtis DURFEE

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L23/532 ,  H01L23/535 ,  H01L21/02 ,  H01L29/40

Abstract: A device including a triple-layer EPI stack including SiGe, Ge, and Si, respectively, with Ga confined therein, and method of production thereof. Embodiments include an EPI stack including a SiGe layer, a Ge layer, and a Si layer over a plurality of fins, the EPI stack positioned between and over a portion of sidewall spacers, wherein the Si layer is a top layer capping the Ge layer, and wherein the Ge layer is a middle layer capping the SiGe layer underneath; and a Ga layer in a portion of the Ge layer between the SiGe layer and the Si layer.

公开(公告)号：US20180006155A1

公开(公告)日：2018-01-04

申请号：US15197892

申请日：2016-06-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Robert Judson HOLT ,  Jinping LIU ,  Jody FRONHEISER ,  Bharat KRISHNAN ,  Churamani GAIRE ,  Timothy James MCARDLE ,  Murat Kerem AKARVARDAR

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/324 ,  H01L21/02 ,  H01L27/088 ,  H01L21/762

CPC classification number: H01L21/02694 ,  H01L21/02236 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/324 ,  H01L21/76224 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/785

Abstract: A method of forming defect-free relaxed SiGe fins is provided. Embodiments include forming fully strained defect-free SiGe fins on a first portion of a Si substrate; forming Si fins on a second portion of the Si substrate; forming STI regions between adjacent SiGe fins and Si fins; forming a cladding layer over top and side surfaces of the SiGe fins and the Si fins and over the STI regions in the second portion of the Si substrate; recessing the STI regions on the first portion of the Si substrate, revealing a bottom portion of the SiGe fins; implanting dopant into the Si substrate below the SiGe fins; and annealing.

公开(公告)号：US20160225852A1

公开(公告)日：2016-08-04

申请号：US14609504

申请日：2015-01-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shishir RAY ,  Bharat KRISHNAN ,  Min-hwa CHI

IPC: H01L29/08 ,  H01L21/268 ,  H01L21/324 ,  H01L29/04 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/268 ,  H01L21/3247 ,  H01L29/045 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7847 ,  H01L29/7848

Abstract: Methods are providing for fabricating transistors having at least one source region or drain region with a stressed portion. The methods include: forming, within a cavity of a substrate structure, the at least one source region or drain region with the internal stress; and resurfacing the at least one source region or drain region to reduce surface defects of the at least one source region or drain region without relaxing the stressed portion thereof. For instance, the resurfacing can include melting an upper portion of the at least one source region or drain region. In addition, the resurfacing can include re-crystallizing an upper portion of the at least one source region or drain region, and/or providing the at least one source region or drain region with at least one {111} surface.

Abstract translation: 提供制造具有至少一个具有应力部分的源极区或漏极区的晶体管的方法。 所述方法包括：在衬底结构的空腔内形成具有内部应力的至少一个源极区域或漏极区域; 以及重新铺展所述至少一个源极区域或漏极区域以减少所述至少一个源极区域或漏极区域的表面缺陷，而不放松其应力部分。 例如，表面重排可以包括熔化至少一个源区或漏区的上部。 另外，重新表面可以包括重新结晶至少一个源区或漏区的上部，和/或向至少一个源区或漏区提供至少一个{111}表面。

公开(公告)号：US20150123146A1

公开(公告)日：2015-05-07

申请号：US14071170

申请日：2013-11-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bharat KRISHNAN ,  Jody A. FRONHEISER ,  Jinping LIU ,  Bongki LEE

IPC: H01L21/02 ,  H01L29/165 ,  H01L29/78 ,  H01L29/06 ,  H01L29/16

CPC classification number: H01L21/823431 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/02587 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/324 ,  H01L29/0657 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor structure includes a bulk silicon substrate and one or more silicon fins coupled to the bulk silicon substrate. Stress-inducing material(s), such as silicon, are epitaxially grown on the fins into naturally diamond-shaped structures using a controlled selective epitaxial growth. The diamond shaped structures are subjected to annealing at about 750° C. to about 850° C. to increase an area of (100) surface orientation by reshaping the shaped structures from the annealing. Additional epitaxy is grown on the increased (100) area. Multiple cycles of increasing the area of (100) surface orientation (e.g., by the annealing) and growing additional epitaxy on the increased area are performed to decrease the width of the shaped structures, increasing the space between them to prevent them from merging, while also increasing their volume.

Abstract translation: 半导体结构包括体硅衬底和耦合到体硅衬底的一个或多个硅散热片。 使用受控的选择性外延生长，诸如硅的应力诱导材料在翅片上外延生长成天然的菱形结构。 金刚石结构在约750℃至约850℃下进行退火，以通过从退火中重塑成形结构来增加（100）表面取向的面积。 额外的外延生长在增加的（100）区域。 进行增加（100）表面取向（例如通过退火）的面积和在增加的面积上生长附加外延的多个循环以减小成形结构的宽度，增加它们之间的空间以防止它们的合并，同时 也增加了他们的体积。