公开(公告)号：US20150064903A1

公开(公告)日：2015-03-05

申请号：US14015640

申请日：2013-08-30

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES, Inc.

Inventor： Kunaljeet Tanwar ,  Xunyuan Zhang ,  Donald Canaperi ,  Raghuveer Patlolla

IPC: H01L21/306

CPC classification number: H01L21/3212 ,  H01L21/32115 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/7688 ,  H01L21/76883

Abstract: Methods for fabricating integrated circuits using chemical mechanical planarization (CMP) for recessing metal are provided. In an embodiment, a method for fabricating an integrated circuit includes filling a trench with a metal and forming an overburden portion of the metal outside of the trench. The method further includes performing a planarization process with an etching slurry to remove the overburden portion of the metal and to recess the metal within the trench.

Abstract translation: 提供了使用用于凹陷金属的化学机械平面化（CMP）的集成电路的方法。 在一个实施例中，用于制造集成电路的方法包括用金属填充沟槽并在沟槽外部形成金属的覆盖层部分。 该方法还包括用蚀刻浆料进行平坦化处理以去除金属的覆盖层部分并使沟槽内的金属凹陷。

公开(公告)号：US08883020B2

公开(公告)日：2014-11-11

申请号：US13754170

申请日：2013-01-30

Applicant: Globalfoundries, Inc.

Inventor： Xunyuan Zhang ,  Xiuyu Cai

IPC: B44C1/22 ,  H05K3/00

CPC classification number: H01L21/3212 ,  C09G1/02 ,  H01L21/283 ,  H01L21/32115 ,  H01L21/7684 ,  H01L21/76888 ,  H01L23/53228 ,  H01L45/1633 ,  H01L2924/0002 ,  H05K3/00 ,  H05K3/26 ,  H05K2201/0376 ,  H05K2203/0346 ,  H01L2924/00

Abstract: Greater planarity is achieved between surfaces of a conductive structure and a layer within which the conductive structure resides. A portion of the conductive structure protruding above the surface of the layer is selectively oxidized, at least in part, to form an oxidized portion. The oxidized portion is then removed, at least partially, to facilitate achieving greater planarity. The protruding portions may optionally be formed by selectively disposing conductive material over the conductive structure, when that the conductive structure is initially recessed below the surface of the layer. A further embodiment includes selectively oxidizing a portion of the conductive structure below the surface of the layer, removing at least some of the oxidized portion so that an upper surface of the conductive structure is below the upper surface of the layer, and planarizing the upper surface of the layer to the upper surface of the conductive structure.

Abstract translation: 在导电结构的表面和导电结构所在的层之间实现更大的平坦度。 突出在层表面之上的导电结构的一部分被至少部分地选择性地氧化以形成氧化部分。 至少部分地去除氧化部分，以便于实现更大的平坦度。 当导电结构最初凹陷在层的表面下方时，可以可选地通过在导电结构上方选择性地设置导电材料来形成突出部分。 另一个实施例包括选择性地将导电结构的一部分氧化在该层的表面之下，去除至少一些氧化部分，使得导电结构的上表面在该层的上表面之下，并平坦化上表面 的层到导电结构的上表面。

公开(公告)号：US08877633B2

公开(公告)日：2014-11-04

申请号：US13852084

申请日：2013-03-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Hoon Kim ,  Vivian W. Ryan

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L23/5226 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76858 ,  H01L21/76859 ,  H01L23/53214 ,  H01L23/53219 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53261 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a barrier system comprised of at least one barrier material and at least two metallic elements, and performing a heating process to form a metal alloy comprised of the at least two metallic elements in the barrier system. Also disclosed is a device that comprises a trench/via in a layer of insulating material, a barrier system positioned in the trench/via, wherein the barrier system comprises at least one barrier material and a metal alloy comprised of at least two metallic elements that are comprised of materials other than the at least one barrier material, and a conductive structure positioned in the trench/via above the barrier system.

Abstract translation: 本文公开的一种说明性方法包括在绝缘材料层中形成沟槽/通孔，形成由至少一种阻挡材料和至少两种金属元素组成的阻挡系统，并且进行加热工艺以形成由 屏障系统中至少有两个金属元素。 还公开了一种装置，其包括绝缘材料层中的沟槽/通孔，位于沟槽/通孔中的阻挡系统，其中阻挡系统包括至少一种阻挡材料和由至少两个金属元素组成的金属合金， 由至少一种阻挡材料以外的材料构成，以及位于屏障系统上方的沟槽/通孔中的导电结构。

公开(公告)号：US08753975B1

公开(公告)日：2014-06-17

申请号：US13757288

申请日：2013-02-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Larry Zhao ,  Ming He ,  Sean Lin ,  John Iacoponi ,  Errol Todd Ryan

IPC: H01L21/4763

CPC classification number: H01L21/76873 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76856 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method includes forming a trench/via in a layer of insulating material, forming a first layer comprised of silicon or germanium on the insulating material in the trench/via, forming a copper-based seed layer on the first layer, converting at least a portion of the copper-based seed layer into a copper-based nitride layer, depositing a bulk copper-based material on the copper-based nitride layer so as to overfill the trench/via and performing at least one chemical mechanical polishing process to remove excess materials positioned outside of the trench/via to thereby define a copper-based conductive structure. A device includes a layer of insulating material, a copper-based conductive structure positioned in a trench/via within the layer of insulating material and a copper-based nitride layer positioned between the copper-based conductive structure and the layer of insulating material, wherein the copper-based nitride layer contacts both of the copper-based conductive structure and the layer of insulating material.

Abstract translation: 一种方法包括在绝缘材料层中形成沟槽/通孔，在沟槽/通孔中的绝缘材料上形成由硅或锗构成的第一层，在第一层上形成铜基种子层，至少转化为 铜基种子层的一部分成为铜基氮化物层，在铜基氮化物层上沉积大量铜基材料，以覆盖沟槽/通孔，并执行至少一种化学机械抛光工艺以除去过量的 位于沟槽/通孔外部的材料，从而限定铜基导电结构。 一种器件包括绝缘材料层，位于绝缘材料层内的沟槽/通孔中的铜基导电结构以及位于铜基导电结构和绝缘材料层之间的铜基氮化物层，其中 铜基氮化物层接触铜基导电结构和绝缘材料层。

公开(公告)号：US20140138779A1

公开(公告)日：2014-05-22

申请号：US13682331

申请日：2012-11-20

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Xunyuan Zhang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/40

CPC classification number: H01L29/66545 ,  H01L21/28114 ,  H01L29/401 ,  H01L29/4991 ,  H01L29/66553 ,  H01L29/66628 ,  H01L29/78

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a sacrificial gate structure over a semiconductor substrate. A spacer is formed around the sacrificial gate structure and a dielectric material is deposited over the spacer and semiconductor substrate. The method includes selectively etching the spacer to form a trench between the sacrificial gate structure and the dielectric material. The trench is bounded by a trench surface upon which a replacement spacer material is deposited. The method merges an upper region of the replacement spacer material to enclose a void within the replacement spacer material.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个实施例中，一种用于制造集成电路的方法包括在半导体衬底上形成牺牲栅极结构。 在牺牲栅极结构周围形成间隔物，并且在间隔物和半导体衬底上沉积电介质材料。 该方法包括选择性地蚀刻间隔物以在牺牲栅极结构和电介质材料之间形成沟槽。 沟槽由沟槽表面限定，在该沟槽表面上沉积替代间隔物材料。 该方法合并替换间隔物材料的上部区域以在替换间隔物材料内包围空隙。

公开(公告)号：USRE49820E1

公开(公告)日：2024-01-30

申请号：US16558106

申请日：2019-08-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Larry Zhao ,  Ming He ,  Xunyuan Zhang ,  Sean Xuan Lin

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76831 ,  H01L21/76846 ,  H01L21/76855 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An approach for forming a semiconductor device is provided. In general, the device is formed by providing a metal layer, a cap layer over the metal layer, and an ultra low k layer over the cap layer. A via is then formed through the ultra low k layer and the cap layer. Once the via is formed, a barrier layer (e.g., cobalt (Co), tantalum (Ta), cobalt-tungsten-phosphide (CoWP), or other metal capable of acting as a copper (CU) diffusion barrier) is selectively applied to a bottom surface of the via. A liner layer (e.g., manganese (MN) or aluminum (AL)) is then applied to a set of sidewalls of the via. The via may then be filled with a subsequent metal layer (with or without a seed layer), and the device may the then be further processed (e.g., annealed).

公开(公告)号：US10553478B2

公开(公告)日：2020-02-04

申请号：US16049303

申请日：2018-07-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xunyuan Zhang ,  Moosung M. Chae

IPC: H01L21/768 ,  H01L21/8234 ,  H01L23/528 ,  H01L29/40 ,  H01L29/417 ,  H01L29/45

Abstract: Embodiments of the present disclosure may provide a method of forming an integrated circuit (IC) structure, the method including: forming a doped metal layer within a contact opening in an inter-level dielectric (ILD) material on a conductive region, such that the doped metal layer overlies the conductive region, the doped metal layer including a first metal doped with a second metal; and forming a contact to the conductive region within the contact opening of the ILD material by annealing the doped metal layer such that the second metal diffuses into the ILD material to form an interface liner directly between the annealed doped metal layer and the ILD material, the interface liner formed only on sidewalls of the contact opening and in direct contact with the ILD material and only at an interface of the doped metal layer and the ILD material.

公开(公告)号：USRE47630E1

公开(公告)日：2019-10-01

申请号：US15335313

申请日：2016-10-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Larry Zhao ,  Ming He ,  Xunyuan Zhang ,  Sean Xuan Lin

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/768 ,  H01L23/48

Abstract: An approach for forming a semiconductor device is provided. In general, the device is formed by providing a metal layer, a cap layer over the metal layer, and an ultra low k layer over the cap layer. A via is then formed through the ultra low k layer and the cap layer. Once the via is formed, a barrier layer (e.g., cobalt (Co), tantalum (Ta), cobalt-tungsten-phosphide (CoWP), or other metal capable of acting as a copper (CU) diffusion barrier) is selectively applied to a bottom surface of the via. A liner layer (e.g., manganese (MN) or aluminum (AL)) is then applied to a set of sidewalls of the via. The via may then be filled with a subsequent metal layer (with or without a seed layer), and the device may the then be further processed (e.g., annealed).

公开(公告)号：US10283608B2

公开(公告)日：2019-05-07

申请号：US15461634

申请日：2017-03-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xunyuan Zhang ,  Frank Mont ,  Mark Raymond ,  Chengyu Niu

IPC: H01L21/4763 ,  H01L21/70 ,  H01L29/45 ,  H01L29/66 ,  H01L21/28 ,  H01L29/08 ,  H01L21/768 ,  H01L21/285 ,  H01L29/78 ,  H01L29/417

Abstract: A conductive source/drain contact is formed within a trench overlying a raised epitaxial source/drain junction. The conductive contact includes a conductive liner and a conductive fill material formed directly over the conductive liner. The conductive fill material is selected from a platinum group metal such as ruthenium. The conductive liner may be directionally deposited into the trench and is adapted to form a metal silicide in situ through a reaction with the epitaxial layer.

公开(公告)号：US10283372B2

公开(公告)日：2019-05-07

申请号：US15705956

申请日：2017-09-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sean Xuan Lin ,  Xunyuan Zhang ,  Mark V. Raymond ,  Errol Todd Ryan ,  Nicholas V. LiCausi

IPC: H01L27/10 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/532

Abstract: Methods of forming interconnects. An interconnect opening is formed in a dielectric layer. A first conductor layer composed of a first metal is formed in the interconnect opening. A second conductor layer is formed inside the interconnect opening by displacing the first metal of the first conductor layer and replacing the first metal with a second metal different from the first metal.