公开(公告)号：US20110039383A1

公开(公告)日：2011-02-17

申请号：US12583192

申请日：2009-08-14

申请人： John Chen ,  Il Kwan Lee ,  Hong Chang ,  Wenjun Li ,  Anup Bhalla ,  Hamza Yilmaz

发明人： John Chen ,  Il Kwan Lee ,  Hong Chang ,  Wenjun Li ,  Anup Bhalla ,  Hamza Yilmaz

IPC分类号： H01L21/8234

CPC分类号： H01L29/7811 ,  H01L21/26586 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

摘要： A method for fabricating a semiconductor device includes forming a plurality of trenches, including applying a first mask, forming a first polysilicon region in at least some of the plurality of trenches, forming a inter-polysilicon dielectric region and a termination protection region, including applying a second mask, forming a second polysilicon region in the at least some of the plurality of trenches, forming a first electrical contact to the first polysilicon region and forming a second electrical contact to the second polysilicon region, including applying a third mask, disposing a metal layer, and forming a source metal region and a gate metal region, including applying a fourth mask.

摘要翻译： 一种制造半导体器件的方法包括形成多个沟槽，包括施加第一掩模，在多个沟槽中的至少一些沟槽中形成第一多晶硅区域，形成多晶硅间介质区域和端接保护区域，包括施加 第二掩模，在所述多个沟槽中的所述至少一些沟槽中形成第二多晶硅区域，形成到所述第一多晶硅区域的第一电接触并且形成到所述第二多晶硅区域的第二电接触，包括施加第三掩模， 金属层，并且形成源极金属区域和栅极金属区域，包括施加第四掩模。

公开(公告)号：US20110140167A1

公开(公告)日：2011-06-16

申请号：US13024256

申请日：2011-02-09

申请人： Hamza Yilmaz ,  Xiaobin Wang ,  Anup Bhalla ,  John Chen ,  Hong Chang

发明人： Hamza Yilmaz ,  Xiaobin Wang ,  Anup Bhalla ,  John Chen ,  Hong Chang

IPC分类号： H01L29/739 ,  H01L21/331

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L29/0692 ,  H01L29/1095 ,  H01L29/6609 ,  H01L29/66143 ,  H01L29/66348 ,  H01L29/66666 ,  H01L29/7397 ,  H01L29/861 ,  H01L29/872

摘要： A method for forming a semiconductor device includes forming a nanotube region using a thin epitaxial layer formed on the sidewall of a trench in the semiconductor body. The thin epitaxial layer has uniform doping concentration. In another embodiment, a first thin epitaxial layer of the same conductivity type as the semiconductor body is formed on the sidewall of a trench in the semiconductor body and a second thin epitaxial layer of the opposite conductivity type is formed on the first epitaxial layer. The first and second epitaxial layers have uniform doping concentration. The thickness and doping concentrations of the first and second epitaxial layers and the semiconductor body are selected to achieve charge balance. In one embodiment, the semiconductor body is a lightly doped P-type substrate. A vertical trench MOSFET, an IGBT, a Schottky diode and a P-N junction diode can be formed using the same N-Epi/P-Epi nanotube structure.

摘要翻译： 形成半导体器件的方法包括：使用形成在半导体本体中的沟槽的侧壁上的薄外延层来形成纳米管区域。 薄的外延层具有均匀的掺杂浓度。 在另一个实施例中，在半导体主体中的沟槽的侧壁上形成与半导体本体相同的导电类型的第一薄外延层，并且在第一外延层上形成相反导电类型的第二薄外延层。 第一和第二外延层具有均匀的掺杂浓度。 选择第一和第二外延层和半导体本体的厚度和掺杂浓度以实现电荷平衡。 在一个实施例中，半导体本体是轻掺杂的P型衬底。 可以使用相同的N-Epi / P-Epi纳米管结构形成垂直沟槽MOSFET，IGBT，肖特基二极管和P-N结二极管。

公开(公告)号：US20110068386A1

公开(公告)日：2011-03-24

申请号：US12565611

申请日：2009-09-23

申请人： Sung-Shan Tai ,  Hamza Yilmaz ,  Anup Bhalla ,  Hong Chang ,  John Chen

发明人： Sung-Shan Tai ,  Hamza Yilmaz ,  Anup Bhalla ,  Hong Chang ,  John Chen

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L29/0869 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： A semiconductor device and a method for making a semiconductor device are disclosed. A trench mask may be applied to a semiconductor substrate, which is etched to form trenches with three different widths. A first conductive material is formed at the bottom of the trenches. A second conductive material is formed over the first conductive material. An insulator layer separates the first and second conductive materials. A first insulator layer is deposited on top of the trenches. A body layer is formed in a top portion of the substrate. A source is formed in the body layer. A second insulator layer is applied on top of the trenches and the source. A contact mask is applied on top of the second insulator layer. Source and gate contacts are formed through the second insulator layer. Source and gate metal are formed on top of the second insulator layer.

摘要翻译： 公开了半导体器件和制造半导体器件的方法。 可以将沟槽掩模施加到半导体衬底，其被蚀刻以形成具有三个不同宽度的沟槽。 第一导电材料形成在沟槽的底部。 在第一导电材料上形成第二导电材料。 绝缘体层分离第一和第二导电材料。 第一绝缘体层沉积在沟槽的顶部。 主体层形成在基板的顶部。 源体形成在体层中。 第二绝缘体层被施加在沟槽和源的顶部上。 接触掩模施加在第二绝缘体层的顶部。 源极和栅极触点通过第二绝缘体层形成。 源极和栅极金属形成在第二绝缘体层的顶部上。

公开(公告)号：US08299494B2

公开(公告)日：2012-10-30

申请号：US12484170

申请日：2009-06-12

申请人： Hamza Yilmaz ,  Xiaobin Wang ,  Anup Bhalla ,  John Chen ,  Hong Chang

发明人： Hamza Yilmaz ,  Xiaobin Wang ,  Anup Bhalla ,  John Chen ,  Hong Chang

IPC分类号： H01L29/74 ,  H01L31/111 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L29/0886 ,  H01L21/26586 ,  H01L27/0623 ,  H01L27/0629 ,  H01L27/0664 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0676 ,  H01L29/0688 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/365 ,  H01L29/402 ,  H01L29/404 ,  H01L29/41741 ,  H01L29/41775 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7803 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/861 ,  H01L29/8613 ,  H01L29/872 ,  H01L29/8725

摘要： A semiconductor device includes a first semiconductor layer and a second semiconductor layer of opposite conductivity type, a first epitaxial layer of the first conductivity type formed on sidewalls of the trenches, and a second epitaxial layer of the second conductivity type formed on the first epitaxial layer where the second epitaxial layer is electrically connected to the second semiconductor layer. The first epitaxial layer and the second epitaxial layer form parallel doped regions along the sidewalls of the trenches, each having uniform doping concentration. The second epitaxial layer has a first thickness and a first doping concentration and the first epitaxial layer and a mesa of the first semiconductor layer together having a second thickness and a second average doping concentration where the first and second thicknesses and the first doping concentration and second average doping concentrations are selected to achieve charge balance in operation.

摘要翻译： 半导体器件包括第一半导体层和相反导电类型的第二半导体层，形成在沟槽的侧壁上的第一导电类型的第一外延层和形成在第一外延层上的第二导电类型的第二外延层 其中第二外延层电连接到第二半导体层。 第一外延层和第二外延层沿着沟槽的侧壁形成平行的掺杂区域，每个具有均匀的掺杂浓度。 第二外延层具有第一厚度和第一掺杂浓度，第一外延层和第一半导体层的台面一起具有第二厚度和第二平均掺杂浓度，其中第一和第二厚度和第一掺杂浓度和第二掺杂浓度 选择平均掺杂浓度以在操作中实现电荷平衡。

公开(公告)号：US08236651B2

公开(公告)日：2012-08-07

申请号：US12583192

申请日：2009-08-14

申请人： John Chen ,  Il Kwan Lee ,  Hong Chang ,  Wenjun Li ,  Anup Bhalla ,  Hamza Yilmaz

发明人： John Chen ,  Il Kwan Lee ,  Hong Chang ,  Wenjun Li ,  Anup Bhalla ,  Hamza Yilmaz

IPC分类号： H01L21/8234

CPC分类号： H01L29/7811 ,  H01L21/26586 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

摘要： A method for fabricating a semiconductor device includes forming a plurality of trenches, including applying a first mask, forming a first polysilicon region in at least some of the plurality of trenches, forming a inter-polysilicon dielectric region and a termination protection region, including applying a second mask, forming a second polysilicon region in the at least some of the plurality of trenches, forming a first electrical contact to the first polysilicon region and forming a second electrical contact to the second polysilicon region, including applying a third mask, disposing a metal layer, and forming a source metal region and a gate metal region, including applying a fourth mask.

摘要翻译： 一种制造半导体器件的方法包括形成多个沟槽，包括施加第一掩模，在多个沟槽中的至少一些沟槽中形成第一多晶硅区域，形成多晶硅间介质区域和端接保护区域，包括施加 第二掩模，在所述多个沟槽中的所述至少一些沟槽中形成第二多晶硅区域，形成到所述第一多晶硅区域的第一电接触并且形成到所述第二多晶硅区域的第二电接触，包括施加第三掩模， 金属层，并且形成源极金属区域和栅极金属区域，包括施加第四掩模。

公开(公告)号：US08187939B2

公开(公告)日：2012-05-29

申请号：US12565611

申请日：2009-09-23

申请人： Sung-Shan Tai ,  Hamza Yilmaz ,  Anup Bhalla ,  Hong Chang ,  John Chen

发明人： Sung-Shan Tai ,  Hamza Yilmaz ,  Anup Bhalla ,  Hong Chang ,  John Chen

IPC分类号： H01L21/336 ,  H01L29/66

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L29/0869 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： A semiconductor device and a method for making a semiconductor device are disclosed. A trench mask may be applied to a semiconductor substrate, which is etched to form trenches with three different widths. A first conductive material is formed at the bottom of the trenches. A second conductive material is formed over the first conductive material. An insulator layer separates the first and second conductive materials. A first insulator layer is deposited on top of the trenches. A body layer is formed in a top portion of the substrate. A source is formed in the body layer. A second insulator layer is applied on top of the trenches and the source. A contact mask is applied on top of the second insulator layer. Source and gate contacts are formed through the second insulator layer. Source and gate metal are formed on top of the second insulator layer.

摘要翻译： 公开了半导体器件和制造半导体器件的方法。 可以将沟槽掩模施加到半导体衬底，其被蚀刻以形成具有三个不同宽度的沟槽。 第一导电材料形成在沟槽的底部。 在第一导电材料上形成第二导电材料。 绝缘体层分离第一和第二导电材料。 第一绝缘体层沉积在沟槽的顶部。 主体层形成在基板的顶部。 源体形成在体层中。 第二绝缘体层被施加在沟槽和源的顶部上。 接触掩模施加在第二绝缘体层的顶部。 源极和栅极触点通过第二绝缘体层形成。 源极和栅极金属形成在第二绝缘体层的顶部上。

公开(公告)号：US20100317158A1

公开(公告)日：2010-12-16

申请号：US12484166

申请日：2009-06-12

申请人： Hamza Yilmaz ,  Xiaobin Wang ,  Anup Bhalla ,  John Chen ,  Hong Chang

发明人： Hamza Yilmaz ,  Xiaobin Wang ,  Anup Bhalla ,  John Chen ,  Hong Chang

IPC分类号： H01L21/336 ,  H01L21/331 ,  H01L21/329

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L29/0692 ,  H01L29/1095 ,  H01L29/6609 ,  H01L29/66143 ,  H01L29/66348 ,  H01L29/66666 ,  H01L29/7397 ,  H01L29/861 ,  H01L29/872

摘要： A method for forming a semiconductor device includes forming a nanotube region using a thin epitaxial layer formed on the sidewall of a trench in the semiconductor body. The thin epitaxial layer has uniform doping concentration. In another embodiment, a first thin epitaxial layer of the same conductivity type as the semiconductor body is formed on the sidewall of a trench in the semiconductor body and a second thin epitaxial layer of the opposite conductivity type is formed on the first epitaxial layer. The first and second epitaxial layers have uniform doping concentration. The thickness and doping concentrations of the first and second epitaxial layers and the semiconductor body are selected to achieve charge balance. In one embodiment, the semiconductor body is a lightly doped P-type substrate. A vertical trench MOSFET, an IGBT, a Schottky diode and a P-N junction diode can be formed using the same N-Epi/P-Epi nanotube structure.

摘要翻译： 形成半导体器件的方法包括：使用形成在半导体本体中的沟槽的侧壁上的薄外延层来形成纳米管区域。 薄的外延层具有均匀的掺杂浓度。 在另一个实施例中，在半导体主体中的沟槽的侧壁上形成与半导体本体相同的导电类型的第一薄外延层，并且在第一外延层上形成相反导电类型的第二薄外延层。 第一和第二外延层具有均匀的掺杂浓度。 选择第一和第二外延层和半导体本体的厚度和掺杂浓度以实现电荷平衡。 在一个实施例中，半导体本体是轻掺杂的P型衬底。 可以使用相同的N-Epi / P-Epi纳米管结构形成垂直沟槽MOSFET，IGBT，肖特基二极管和P-N结二极管。

公开(公告)号：US20100314659A1

公开(公告)日：2010-12-16

申请号：US12484170

申请日：2009-06-12

申请人： Hamza Yilmaz ,  Xiaobin Wang ,  Anup Bhalla ,  John Chen ,  Hong Chang

发明人： Hamza Yilmaz ,  Xiaobin Wang ,  Anup Bhalla ,  John Chen ,  Hong Chang

IPC分类号： H01L29/739 ,  H01L29/78

CPC分类号： H01L29/0886 ,  H01L21/26586 ,  H01L27/0623 ,  H01L27/0629 ,  H01L27/0664 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0676 ,  H01L29/0688 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/365 ,  H01L29/402 ,  H01L29/404 ,  H01L29/41741 ,  H01L29/41775 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7803 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/861 ,  H01L29/8613 ,  H01L29/872 ,  H01L29/8725

摘要： A semiconductor device includes a first semiconductor layer and a second semiconductor layer of opposite conductivity type, a first epitaxial layer of the first conductivity type formed on sidewalls of the trenches, and a second epitaxial layer of the second conductivity type formed on the first epitaxial layer where the second epitaxial layer is electrically connected to the second semiconductor layer. The first epitaxial layer and the second epitaxial layer form parallel doped regions along the sidewalls of the trenches, each having uniform doping concentration. The second epitaxial layer has a first thickness and a first doping concentration and the first epitaxial layer and a mesa of the first semiconductor layer together having a second thickness and a second average doping concentration where the first and second thicknesses and the first doping concentration and second average doping concentrations are selected to achieve charge balance in operation.

摘要翻译： 半导体器件包括第一半导体层和相反导电类型的第二半导体层，形成在沟槽的侧壁上的第一导电类型的第一外延层和形成在第一外延层上的第二导电类型的第二外延层 其中第二外延层电连接到第二半导体层。 第一外延层和第二外延层沿着沟槽的侧壁形成平行的掺杂区域，每个具有均匀的掺杂浓度。 第二外延层具有第一厚度和第一掺杂浓度，第一外延层和第一半导体层的台面一起具有第二厚度和第二平均掺杂浓度，其中第一和第二厚度和第一掺杂浓度和第二掺杂浓度 选择平均掺杂浓度以在操作中实现电荷平衡。

公开(公告)号：US09647059B2

公开(公告)日：2017-05-09

申请号：US14298922

申请日：2014-06-08

申请人： Lingping Guan ,  Madhur Bobde ,  Anup Bhalla ,  Yeeheng Lee ,  John Chen ,  Moses Ho

发明人： Lingping Guan ,  Madhur Bobde ,  Anup Bhalla ,  Yeeheng Lee ,  John Chen ,  Moses Ho

IPC分类号： H01L21/8238 ,  H01L29/06 ,  H01L21/225 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L21/266

CPC分类号： H01L29/0634 ,  H01L21/2253 ,  H01L21/266 ,  H01L21/324 ,  H01L29/1095 ,  H01L29/66712 ,  H01L29/7802

摘要： This invention discloses a method for manufacturing a semiconductor power device on a semiconductor substrate supporting a drift region composed of an epitaxial layer. The method includes a first step of growing a first epitaxial layer followed by forming a first hard mask layer on top of the epitaxial layer; a second step of applying a first implant mask to open a plurality of implant windows and applying a second implant mask for blocking some of the implant windows to implant a plurality of dopant regions of alternating conductivity types adjacent to each other in the first epitaxial layer; and a third step of repeating the first step and the second step by applying the same first and second implant masks to form a plurality of epitaxial layers, each of which is implanted with the dopant regions of the alternating conductivity types. Then the manufacturing processes proceed by carrying out a device manufacturing process on a top side of the epitaxial layer on top of the dopant regions of the alternating conductivity types with a diffusion process to merge the dopant regions of the alternating conductivity types as doped columns in the epitaxial layers.

公开(公告)号：US20130001695A1

公开(公告)日：2013-01-03

申请号：US13171037

申请日：2011-06-28

申请人： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla

发明人： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L27/0262 ,  H01L21/8222 ,  H01L27/0255 ,  H01L27/0259 ,  H01L27/0814 ,  H01L27/082

摘要： An epitaxial layer is supported on top of a substrate. First and second body regions are formed within the epitaxial layer separated by a predetermined lateral distance. Trigger and source regions are formed within the epitaxial layer. A first source region is transversely adjacent the first body region between first and second trigger regions laterally adjacent the first source region and transversely adjacent the first body region. A second source region is located transversely adjacent the second body region between third and fourth trigger regions laterally adjacent the second source region and transversely adjacent the second body region. A third source region is laterally adjacent the fourth trigger region. The fourth trigger region is between the second and third source regions. An implant region within the fourth trigger region is laterally adjacent the third source region.

摘要翻译： 外延层支撑在基板的顶部。 第一和第二体区域形成在外延层中以预定的横向距离分开。 在外延层内形成触发源区和源极区。 第一源区域横向地邻近第一和第二触发区域之间的与第一源区域相邻并且横向邻近第一体区域的第一体区域相邻。 第二源区域横向地邻近第二和第四触发区域之间的第二体区横向邻近第二源区域并且横向邻近第二体区域定位。 第三源区域与第四触发区域横向相邻。 第四触发区域在第二和第三源区之间。 第四触发区域内的植入区域与第三源区域横向相邻。