公开(公告)号：US20060142988A1

公开(公告)日：2006-06-29

申请号：US11318431

申请日：2005-12-28

申请人： Satoru Akiyama ,  Tomonori Sekiguchi ,  Takayuki Kawahara ,  Kazuhiko Kajigaya

发明人： Satoru Akiyama ,  Tomonori Sekiguchi ,  Takayuki Kawahara ,  Kazuhiko Kajigaya

IPC分类号： G06F17/50

CPC分类号： G06F17/5009 ,  G06F2217/10 ,  G06F2217/78

摘要： A manufacturing method for semiconductor memory and a semiconductor design device, which can facilitate design and reduce a period of time required for the design, are provided. For example, when a designed memory array is verified, a read-out signal of a memory cell formulated by functions of respective parameters having various distributions is used. A value of the read-out signal is calculated by using a value extracted randomly from the distribution for each kind of parameter. Quality of the memory cell is determined from a calculated result. Calculation of the value of the read-out signal and determination of the quality of the memory cell are carried out to a great number of memory cells the memory array has. The total number of failed bits and the like obtained from these is used as an evaluation criterion.

摘要翻译： 提供一种半导体存储器和半导体设计装置的制造方法，其可以促进设计并减少设计所需的时间。 例如，当设计的存储器阵列被验证时，使用由具有各种分布的各个参数的功能所制定的存储器单元的读出信号。 通过使用从各种参数的分布中随机提取的值来计算读出信号的值。 从计算结果确定存储单元的质量。 对存储器阵列具有的大量存储单元执行读出信号的值的计算和存储单元的质量的确定。 将从这些获得的故障比特等的总数用作评估标准。

公开(公告)号：US20060024875A1

公开(公告)日：2006-02-02

申请号：US11234118

申请日：2005-09-26

申请人： Makoto Yoshida ,  Takahiro Kumauchi ,  Yoshitaka Tadaki ,  Kazuhiko Kajigaya ,  Hideo Aoki ,  Isamu Asano

发明人： Makoto Yoshida ,  Takahiro Kumauchi ,  Yoshitaka Tadaki ,  Kazuhiko Kajigaya ,  Hideo Aoki ,  Isamu Asano

IPC分类号： H01L21/8234

CPC分类号： H01L21/2652 ,  H01L21/32051 ,  H01L21/32053 ,  H01L21/324 ,  H01L21/76802 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76889 ,  H01L21/76897 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/53257 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10882 ,  H01L27/10894 ,  H01L29/6659 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a process for manufacturing a semiconductor integrated circuit device having a MISFET, in order that a shallow junction between the source/drain of the MISFET and a semiconductor substrate may be realized by reducing the number of heat treatment steps, all conductive films to be deposited on the semiconductor substrate are deposited at a temperature of 500° C. or lower at a step after the MISFET has been formed. Moreover, all insulating films to be deposited over the semiconductor substrate are deposited at a temperature of 500° C. or lower at a step after the MISFET has been formed.

摘要翻译： 在制造具有MISFET的半导体集成电路器件的工艺中，为了通过减少热处理步骤的数量来实现MISFET的源极/漏极与半导体衬底之间的浅结，可以将所有导电膜沉积 在形成MISFET之后的步骤中，在500℃以下的温度下沉积半导体基板。 此外，要沉积在半导体衬底上的所有绝缘膜在形成MISFET之后的步骤中在500℃或更低的温度下沉积。

公开(公告)号：US20050237820A1

公开(公告)日：2005-10-27

申请号：US10995198

申请日：2004-11-24

申请人： Riichiro Takemura ,  Takeshi Sakata ,  Norikatsu Takaura ,  Kazuhiko Kajigaya

发明人： Riichiro Takemura ,  Takeshi Sakata ,  Norikatsu Takaura ,  Kazuhiko Kajigaya

IPC分类号： G11C11/42 ,  G11C5/00 ,  G11C7/00 ,  G11C8/08 ,  G11C11/419 ,  G11C13/02

CPC分类号： G11C13/0069 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1096 ,  G11C8/08 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/004 ,  G11C2213/79

摘要： There is achieved a high-integrated and high-speed nonvolatile memory which can stabilize an operation of a phase-change memory for a short operation cycle time. A latch is provided in a write driver. A change to a high-resistance state of a phase-change element is performed per column cycle by a write-enable signal, and a change to a low-resistance state thereof is performed after a pre-charge command is inputted and concurrently with deactivation of a pre-charge signal. Thereby, a write time to a memory cell in which phase-change resistance is changed to a low-resistance state, and a period from a write operation for changing the phase-change resistance to a high-resistance state to a read operation to the above memory cell can be lengthened without extending the column cycle time, so that the stable write operation is achieved.

摘要翻译： 实现了高集成度和高​​速度的非易失性存储器，其可以在短的操作周期时间内稳定相变存储器的操作。 在写入驱动器中提供锁存器。 通过写使能信号，每列循环执行相变元件的高电阻状态的改变，并且在预充电命令被输入之后执行到其低电阻状态的改变，并且同时具有去激活 的预充电信号。 由此，对相变电阻变为低电阻状态的存储单元的写入时间，以及从相变电阻改变为高电阻状态到读操作的写操作的周期 可以延长上述存储单元，而不延长列周期时间，从而实现稳定的写操作。

公开(公告)号：US06909646B2

公开(公告)日：2005-06-21

申请号：US10627769

申请日：2003-07-28

申请人： Masatoshi Hasegawa ,  Kazuhiko Kajigaya

发明人： Masatoshi Hasegawa ,  Kazuhiko Kajigaya

IPC分类号： G11C11/401 ,  G11C7/00 ,  G11C29/00 ,  G11C29/02 ,  G11C29/04

CPC分类号： G11C29/808 ,  G11C7/18 ,  G11C11/4097 ,  G11C29/02 ,  G11C29/025 ,  G11C29/72 ,  G11C29/80 ,  G11C29/848

摘要： In a bit-line direction, a plurality of memory mats are arranged including a plurality of memory cells respectively coupled to bit lines and word lines, and a sense amplifier array is arranged including a plurality of latch circuits having input/output nodes connected to a half of bit-line pairs separately provided to the memory mats in a region between the memory mats placed in the bit-line direction, thereby making possible to replace with a redundant bit line pair and the corresponding redundant sense amplifier on a basis of each bit-line pair and sense amplifier connected thereto, thereby realizing effective and rational Y-system relief.

摘要翻译： 在位线方向上，多个存储器阵列被布置成包括分别耦合到位线和字线的多个存储器单元，并且读出放大器阵列被布置成包括多个锁存电路，其中输入/输出节点连接到 一半的位线对分别提供给放置在位线方向上的存储器垫之间的区域中的存储器堆，从而可以基于每个位替换冗余位线对和相应的冗余读出放大器 线对和读出放大器，从而实现有效和合理的Y系统释放。

公开(公告)号：US06680875B2

公开(公告)日：2004-01-20

申请号：US10259579

申请日：2002-09-30

申请人： Masashi Horiguchi ,  Masayuki Nakamura ,  Sadayuki Ohkuma ,  Kazuhiko Kajigaya ,  Yoshinobu Nakagome

发明人： Masashi Horiguchi ,  Masayuki Nakamura ,  Sadayuki Ohkuma ,  Kazuhiko Kajigaya ,  Yoshinobu Nakagome

IPC分类号： G11C800

CPC分类号： G11C5/063 ,  G11C5/14 ,  G11C5/147 ,  G11C7/1072 ,  G11C8/12 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/4074 ,  G11C11/4076 ,  G11C2207/2227 ,  G11C2211/4067 ,  G11C2211/4068

摘要： A semiconductor device comprising a plurality of memory banks and a plurality of power supply circuits corresponding to the memory banks. Each of the memory banks is independently activated by an activating command. Given an externally supplied voltage, each of the power supply circuits outputs a predetermined internal supply voltage. Each power supply circuit has its output connected to the corresponding memory bank. In response to a command for activating one of the memory banks, the corresponding power supply circuit is activated while the remaining power supply circuits is deactivated.

摘要翻译： 一种半导体器件，包括多个存储体和对应于存储体的多个电源电路。 每个存储体被激活命令独立地激活。 给定外部提供的电压，每个电源电路输出预定的内部电源电压。 每个电源电路的输出连接到相应的存储体。 响应于用于激活存储体之一的命令，相应的电源电路被激活，而剩余的电源电路被去激活。

公开(公告)号：US06603688B2

公开(公告)日：2003-08-05

申请号：US09811400

申请日：2001-03-20

申请人： Masatoshi Hasegawa ,  Kazuhiko Kajigaya

发明人： Masatoshi Hasegawa ,  Kazuhiko Kajigaya

IPC分类号： G11C700

CPC分类号： G11C29/808 ,  G11C7/18 ,  G11C11/4097 ,  G11C29/02 ,  G11C29/025 ,  G11C29/72 ,  G11C29/80 ,  G11C29/848

摘要： In a bit-line direction, a plurality of memory mats are arranged including a plurality of memory cells respectively coupled to bit lines and word lines, and a sense amplifier array is arranged including a plurality of latch circuits having input/output nodes connected to a half of bit-line pairs separately provided to the memory mats in a region between the memory mats placed in the bit-line direction, thereby making possible to replace with a redundant bit line pair and the corresponding redundant sense amplifier on a basis of each bit-line pair and sense amplifier connected thereto, thereby realizing effective and rational Y-system relief.

摘要翻译： 在位线方向上，多个存储器阵列被布置成包括分别耦合到位线和字线的多个存储器单元，并且读出放大器阵列被布置成包括多个锁存电路，其中输入/输出节点连接到 一半的位线对分别提供给放置在位线方向上的存储器垫之间的区域中的存储器堆，从而可以基于每个位替换冗余位线对和相应的冗余读出放大器 线对和读出放大器，从而实现有效和合理的Y系统释放。

公开(公告)号：US06538912B2

公开(公告)日：2003-03-25

申请号：US10139330

申请日：2002-05-07

申请人： Riichiro Takemura ,  Tomonori Sekiguchi ,  Katsutaka Kimura ,  Kazuhiko Kajigaya ,  Tsugio Takahashi

发明人： Riichiro Takemura ,  Tomonori Sekiguchi ,  Katsutaka Kimura ,  Kazuhiko Kajigaya ,  Tsugio Takahashi

IPC分类号： G11C1100

CPC分类号： H01L27/10894 ,  G11C11/4097 ,  H01L27/10897

摘要： When a phase shift method is used as lithography where sense amplifiers are alternately placed in a one intersecting-point memory capable of implementing a reduction in the area of a DRAM, it was difficult to layout data lines in a boundary region between sense amplifiers and each memory array. Therefore, there is provided a semiconductor device according to the present invention. In the semiconductor device, two data lines continuous within the sub memory arrays or interposed therebetween are connected to the adjacent sense amplifiers as a system for drawing data lines from sub memory arrays (SMA) to sense amplifiers (SA) when the sense amplifiers are alternately placed. Namely, the number of data lines interposed between data lines respectively connected to two adjacent sense amplifiers is set to even numbers (0, 2, 4, . . . ). Owing to the above configuration, a break and a short circuit in a portion where a sense amplifier block and a sub memory array are connected, can be avoided, and a connection layout is facilitated.

公开(公告)号：US06400596B2

公开(公告)日：2002-06-04

申请号：US09725107

申请日：2000-11-29

申请人： Riichiro Takemura ,  Tomonori Sekiguchi ,  Katsutaka Kimura ,  Kazuhiko Kajigaya ,  Tsugio Takahashi

发明人： Riichiro Takemura ,  Tomonori Sekiguchi ,  Katsutaka Kimura ,  Kazuhiko Kajigaya ,  Tsugio Takahashi

IPC分类号： G11C1100

CPC分类号： H01L27/10894 ,  G11C11/4097 ,  H01L27/10897

摘要： When a phase shift method is used as lithography where sense amplifiers are alternately placed in a one intersecting-point memory capable of implementing a reduction in the area of a DRAM, it was difficult to layout data lines in a boundary region between sense amplifiers and each memory array. Therefore, there is provided a semiconductor device according to the present invention. In the semiconductor device, two data lines continuous within the sub memory arrays or interposed therebetween are connected to the adjacent sense amplifiers as a system for drawing data lines from sub memory arrays (SMA) to sense amplifiers (SA) when the sense amplifiers are alternately placed. Namely, the number of data lines interposed between data lines respectively connected to two adjacent sense amplifiers is set to even numbers (0, 2, 4, . . . ). Owing to the above configuration, a break and a short circuit in a portion where a sense amplifier block and a sub memory array are connected, can be avoided, and a connection layout is facilitated.

摘要翻译： 当使用相移方法作为光刻技术时，将读出放大器交替放置在能够实现DRAM面积减小的一个交叉点存储器中，难以在读出放大器与每个读出放大器之间的边界区域中布置数据线 内存阵列 因此，提供了根据本发明的半导体器件。 在半导体器件中，在副存储器阵列内或插入其间的两条数据线被连接到相邻的读出放大器，作为用于当读出放大器交替地从子存储器阵列（SMA）到读出放大器（SA）的数据线绘制的系统 放置 即，分别连接到两个相邻读出放大器的数据线之间的数据线的数目被设置为偶数（0,2,4 ...）。 由于上述结构，可以避免在读出放大器块和子存储器阵列连接的部分中的断路和短路，并且便于连接布局。

公开(公告)号：US06275440B1

公开(公告)日：2001-08-14

申请号：US09729273

申请日：2000-12-05

申请人： Hiromasa Noda ,  Masakazu Aoki ,  Youji Idei ,  Kazuhiko Kajigaya ,  Osamu Nagashima ,  Kiyoo Itoh ,  Masashi Horiguchi ,  Takeshi Sakata

发明人： Hiromasa Noda ,  Masakazu Aoki ,  Youji Idei ,  Kazuhiko Kajigaya ,  Osamu Nagashima ,  Kiyoo Itoh ,  Masashi Horiguchi ,  Takeshi Sakata

IPC分类号： G11C700

摘要： A dynamic RAM is divided into an input circuit block responsive to an input signal supplied from an external terminal, inclusive of an operation start signal, an internal circuit block activated in response to the signal inputted from the input circuit block, and an output circuit block for outputting a signal outputted from the internal circuit block to an external terminal. A plurality of switch MOSFETs are provided in parallel between a power line for applying an operating voltage supplied from an external terminal and an internal power line for a first circuit portion in the internal circuit block, which does not need a storage operation upon reaching its non-operating state. Further, the switch MOSFETs are stepwise turned on in response to controls signals produced by delaying a start signal supplied through the input circuit block in turn, so as to perform the supply of each operating voltage.

公开(公告)号：US06195305B1

公开(公告)日：2001-02-27

申请号：US09288512

申请日：1999-04-08

申请人： Hiroki Fujisawa ,  Kazuhiko Kajigaya ,  Kenichi Fukui ,  Toshikazu Tachibana

发明人： Hiroki Fujisawa ,  Kazuhiko Kajigaya ,  Kenichi Fukui ,  Toshikazu Tachibana

IPC分类号： G11C700

CPC分类号： G11C5/147

摘要： In a semiconductor integrated circuit in which an internal voltage generation circuit operating on a power supply voltage supplied through an external terminal forms either or both of a low voltage and a boosted voltage to operate internal circuits, a first internal circuit operating on the power supply voltage supplied through the external terminal or the boosted voltage formed by the internal voltage generation circuit is constituted by a first MOSFET with a gate insulation film having a large thickness adapted to the power supply voltage or boosted voltage, and a second internal circuit operating on the low voltage is constituted by a second MOSFET with a gate insulation film having a small thickness adapted to the low voltage.