公开(公告)号：US06256254B1

公开(公告)日：2001-07-03

申请号：US09564593

申请日：2000-05-03

申请人： Choong-Keun Kwak ,  Sang-Jib Han

发明人： Choong-Keun Kwak ,  Sang-Jib Han

IPC分类号： G11C800

CPC分类号： G11C8/12 ,  G11C8/10

摘要： A semiconductor memory device includes a plurality of memory cell array blocks, an address transition detecting pulse generator to generate address transition detecting pulse signals by detecting the transition of a plurality of addresses, a global row decoder having a plurality of groups of pre-decoders and a main decoder to generate a plurality of global word line signals of a plurality of memory cell array blocks by decoding the plurality of addresses, and a plurality of block row decoders having a plurality of decoding cells to respond to block control signals for selecting a plurality of memory cell array blocks and a plurality of pulse control signals combined with the address transition detecting pulse signals to output a plurality of global word line signals generated by the global row decoder as a plurality of local word line signals. A plurality of the decoding cells of a plurality of the block row decoders comprises switching transistors or other means to switch the global word line signals into local word line signals in response to a first state of the pulse control signals, and inactive means, e.g. one or more transistors, to put the local word line signals into its inactive state in response to a second state of the pulse control signals, thereby reducing the number of transistors to make up of the decoder for efficient layout.

摘要翻译： 半导体存储器件包括多个存储单元阵列块，地址转换检测脉冲发生器，用于通过检测多个地址的转换来产生地址转换检测脉冲信号;全局行解码器，具有多组预解码器;以及 主解码器，用于通过解码多个地址来生成多个存储单元阵列块的多个全局字线信号;以及多个块行解码器，具有多个解码单元，以响应用于选择多个地址的块控制信号 的存储单元阵列块和与地址转换检测脉冲信号组合的多个脉冲控制信号，以将由全局行解码器产生的多个全局字线信号作为多个本地字线信号输出。 多个块行解码器的多个解码单元包括开关晶体管或其他装置，以响应于脉冲控制信号的第一状态将全局字线信号切换为本地字线信号，以及无效装置，例如， 一个或多个晶体管，以响应于脉冲控制信号的第二状态将本地字线信号置于其非活动状态，从而减少用于有效布局的解码器的晶体管数量。

公开(公告)号：US5999390A

公开(公告)日：1999-12-07

申请号：US122076

申请日：1998-07-24

申请人： Baek-Hyung Cho ,  Choong-Keun Kwak ,  Ho-Geun Shin

发明人： Baek-Hyung Cho ,  Choong-Keun Kwak ,  Ho-Geun Shin

IPC分类号： H01L27/04 ,  G01R31/28 ,  G01R31/3185 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/092 ,  H03K19/003 ,  H03K19/0175 ,  H02H3/18

CPC分类号： H03K19/00315

摘要： A CMOS input buffer for semiconductor devices, that is capable of protecting its MOS transistors from gate oxide breakdown due to the application of high voltage greater than a normal power supply voltage.

摘要翻译： 用于半导体器件的CMOS输入缓冲器，其能够通过施加大于正常电源电压的高电压来保护其MOS晶体管免受栅极氧化物击穿。

公开(公告)号：US5994943A

公开(公告)日：1999-11-30

申请号：US963792

申请日：1997-11-04

申请人： Young-Ho Suh ,  Choong-Keun Kwak ,  Sang-Jib Han

发明人： Young-Ho Suh ,  Choong-Keun Kwak ,  Sang-Jib Han

IPC分类号： G11C11/417 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H03K19/003 ,  H03K19/0175 ,  H03H5/00 ,  H02H3/20

CPC分类号： H01L27/0266

摘要： A data output circuit includes a periphery circuit connected between a supply voltage and a first ground voltage line and an output driver connected between a supply voltage and a second ground voltage line. The periphery circuit receives a first input signal and generates a first output signal on a node responsive to the first input signal, and the output driver receives a second input signal and the first output signal and generates a second output signal on an output pin in response thereto. A discharge circuit is coupled with the first ground voltage line wherein the discharge circuit allows current to flow from the first ground voltage line and wherein the discharge circuit blocks current flow to the first ground voltage line. Related methods are also discussed.

摘要翻译： 数据输出电路包括连接在电源电压和第一接地电压线之间的外围电路以及连接在电源电压和第二接地电压线之间的输出驱动器。 外围电路接收第一输入信号并响应于第一输入信号在节点上产生第一输出信号，并且输出驱动器接收第二输入信号和第一输出信号，并响应于输出引脚产生第二输出信号 到此。 放电电路与第一接地电压线耦合，其中放电电路允许电流从第一接地电压线流出，并且其中放电电路阻止电流流到第一接地电压线。 还讨论了相关方法。

公开(公告)号：US07502251B2

公开(公告)日：2009-03-10

申请号：US11502563

申请日：2006-08-11

申请人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Du-Eung Kim ,  Beak-Hyung Cho

发明人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Du-Eung Kim ,  Beak-Hyung Cho

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C13/0023 ,  G11C2013/0078 ,  G11C2013/0092

摘要： A phase-change cell memory device includes a plurality of phase-change memory cells, an address circuit, a write driver, and a write driver control circuit. The phase-change memory cells each include a volume of material that is programmable between amorphous and crystalline states. The address circuit selects at least one of the memory cells, and the write driver generates a reset pulse current to program a memory cell selected by the address circuit into the amorphous state, and a set pulse current to program the memory cell selected by the address circuit into the crystalline state. The write driver control circuit varies at least one of a pulse width and a pulse count of at least one of the reset and set pulse currents according to a load between the write driver and the memory cell selected by the address circuit.

摘要翻译： 相变单元存储器件包括多个相变存储器单元，地址电路，写入驱动器和写入驱动器控制电路。 相变存储单元各自包括可在非晶态和晶态之间编程的材料体积。 地址电路选择存储单元中的至少一个，并且写入驱动器产生复位脉冲电流以将由地址电路选择的存储单元编程为非晶状态，以及设置脉冲电流以对由地址选择的存储单元进行编程 电路进入结晶状态。 写入驱动器控制电路根据写入驱动器和由地址电路选择的存储器单元之间的负载来改变至少一个复位和设置的脉冲电流的脉冲宽度和脉冲计数中的至少一个。

公开(公告)号：US07426129B2

公开(公告)日：2008-09-16

申请号：US11183613

申请日：2005-07-18

申请人： Byung-Gil Choi ,  Young-Ho Suh ,  Choong-Keun Kwak

发明人： Byung-Gil Choi ,  Young-Ho Suh ,  Choong-Keun Kwak

IPC分类号： G11C5/06

CPC分类号： G11C7/02 ,  G11C7/18

摘要： A true bit line can extend across a memory cell area of the memory device in a first direction and a complementary bit line can extend across the memory cell area in a second direction opposing the first direction, wherein the true bit line and the complementary bit line comprising a bit line pair.

摘要翻译： 真正的位线可以沿第一方向跨越存储器件的存储器单元区域延伸，并且互补位线可以在与第一方向相反的第二方向跨越存储器单元区域延伸，其中真位线和互补位线 包括位线对。

公开(公告)号：US07274586B2

公开(公告)日：2007-09-25

申请号：US11070196

申请日：2005-03-03

申请人： Byung-Gil Choi ,  Du-Eung Kim ,  Choong-Keun Kwak ,  Beak-Hyung Cho

发明人： Byung-Gil Choi ,  Du-Eung Kim ,  Choong-Keun Kwak ,  Beak-Hyung Cho

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C2013/0078 ,  G11C2013/0088 ,  G11C2013/0092

摘要： A method for programming a phase-change memory array and circuit of a phase-change memory device, each having a plurality of phase-change memory cells, may enable all the phase-change memory cells therein to be changed or set at a set resistance state, and may reduce the time needed to change the phase-change memory array to the set resistance state. In the method, a set current pulse having first through nth stages may be applied to the cells of the array to change the cells to the set resistance state. A minimum current level of the set current pulse applied to the phase-change memory cells in any stage may be higher than a reference current level for the cells of the array. A given current level of the set current pulse may be sequentially reduced from stage to stage.

摘要翻译： 一种用于编程相变存储器阵列和相变存储器件的电路的方法，每个相变存储器件具有多个相变存储器单元，可以使其中的所有相变存储器单元能够被改变或设置为设定电阻 状态，并且可以减少将相变存储器阵列改变为设定电阻状态所需的时间。 在该方法中，可以将具有第一至第n个阶段的设定电流脉冲施加到阵列的单元以将单元改变为设定电阻状态。 施加到任何阶段中的相变存储器单元的设定电流脉冲的最小电流电平可以高于阵列的单元的参考电流电平。 设定电流脉冲的给定电流电平可以从一个阶段顺序地减少。

公开(公告)号：US07221611B2

公开(公告)日：2007-05-22

申请号：US11146513

申请日：2005-06-07

申请人： Gong-Heum Han ,  Choong-Keun Kwak ,  Joon-Min Park

发明人： Gong-Heum Han ,  Choong-Keun Kwak ,  Joon-Min Park

IPC分类号： G11C5/14 ,  G11C7/00

CPC分类号： G11C11/417 ,  G11C5/147

摘要： A semiconductor memory device, which has an array of memory cells connected with a plurality of bit line pairs and a plurality of word lines, to perform a read or write operation of data, having low power consumption is provided. The device includes a first power supply for supplying a first power source voltage. Also, a second power supply supplies a second power source voltage having a lower voltage level than the first power source voltage. Further, the device includes a standard ground. An elevated ground circuit provides an elevated ground voltage having a higher voltage level than that of the standard ground. A first power circuit is connected with the first power supply and the standard ground, and operates in response to the first power source voltage. A second power circuit is connected with the second power supply and the elevated ground circuit, and operates in response to the second power source voltage. Thereby, power and chip size can be reduced.

摘要翻译： 提供具有与多个位线对和多个字线连接的存储单元的阵列以执行具有低功耗的数据的读取或写入操作的半导体存储器件。 该装置包括用于提供第一电源电压的第一电源。 此外，第二电源提供具有比第一电源电压低的电压电平的第二电源电压。 此外，该装置包括标准接地。 提升的接地电路提供比标准接地电压高的电压电平的升高的接地电压。 第一电源电路与第一电源和标准接地相连接，并响应于第一电源电压而工作。 第二电源电路与第二电源和升高的接地电路连接，并且响应于第二电源电压而工作。 从而可以降低功率和芯片尺寸。

公开(公告)号：US20050169093A1

公开(公告)日：2005-08-04

申请号：US10919371

申请日：2004-08-17

申请人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Du-Eung Kim ,  Beak-Hyung Cho

发明人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Du-Eung Kim ,  Beak-Hyung Cho

IPC分类号： G11C13/02 ,  G11C8/00 ,  G11C16/02

CPC分类号： G11C13/0004 ,  G11C13/0023 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/79

摘要： A phase-change cell memory device includes a plurality of phase-change memory cells, an address circuit, a write driver, and a write driver control circuit. The phase-change memory cells each include a volume of material that is programmable between amorphous and crystalline states. The address circuit selects at least one of the memory cells, and the write driver generates a reset pulse current to program a memory cell selected by the address circuit into the amorphous state, and a set pulse current to program the memory cell selected by the address circuit into the crystalline state. The write driver control circuit varies at least one of a pulse width and a pulse count of at least one of the reset and set pulse currents according to a load between the write driver and the memory cell selected by the address circuit.

摘要翻译： 相变单元存储器件包括多个相变存储器单元，地址电路，写入驱动器和写入驱动器控制电路。 相变存储单元各自包括可在非晶态和晶态之间编程的材料体积。 地址电路选择存储单元中的至少一个，并且写入驱动器产生复位脉冲电流以将由地址电路选择的存储单元编程为非晶状态，以及设置脉冲电流以对由地址选择的存储单元进行编程 电路进入结晶状态。 写入驱动器控制电路根据写入驱动器和由地址电路选择的存储器单元之间的负载来改变复位和设置脉冲电流中的至少一个的脉冲宽度和脉冲计数中的至少一个。

公开(公告)号：US06870783B2

公开(公告)日：2005-03-22

申请号：US10661581

申请日：2003-09-15

申请人： Choong-Keun Kwak ,  Bo-Tak Lim

发明人： Choong-Keun Kwak ,  Bo-Tak Lim

IPC分类号： G11C5/14 ,  G11C7/10 ,  G11C11/4193 ,  G11C29/46

CPC分类号： G11C7/1045 ,  G11C29/46

摘要： In a mode entrance control circuit and a mode entering method to stably enter a semiconductor memory device into a predetermined operating mode only when insensitive to a change of a process, temperature, or voltage, etc., and simultaneously satisfying a constant entrance condition, the mode entrance control circuit includes an operation control part for generating an operation enable signal when a first voltage applied through a first pad is over a first determination voltage, a voltage division part for dividing a second voltage applied through a second pad to generate a trimming reference voltage, and a mode entrance signal generating part operated in response to the operation enable signal, for comparing a level of an applied fixed reference voltage with a level of the trimming reference voltage, and for generating a mode entrance enable signal to allow the semiconductor memory device to enter into a predetermined mode.

摘要翻译： 在模式入口控制电路和模式输入方法中，只有当对过程，温度或电压等的改变不敏感并且同时满足恒定的入口条件时，才能将半导体存储器件稳定地进入预定的操作模式， 模式入口控制电路包括：操作控制部分，用于当通过第一焊盘施加的第一电压超过第一确定电压时产生操作使能信号;分压部分，用于分割通过第二焊盘施加的第二电压，以产生修整参考 电压和模式入口信号产生部件，其响应于所述操作使能信号而被操作，用于将所施加的固定参考电压的电平与所述修整参考电压的电平进行比较，并且用于产生模式入口使能信号以允许所述半导体存储器 设备进入预定模式。

公开(公告)号：US06288926B1

公开(公告)日：2001-09-11

申请号：US09535871

申请日：2000-03-27

申请人： Du-Eung Kim ,  Byung-Gil Choi ,  Sang-Jib Han ,  Choong-Keun Kwak ,  Soon-Moon Jung ,  Sung-Bong Kim

发明人： Du-Eung Kim ,  Byung-Gil Choi ,  Sang-Jib Han ,  Choong-Keun Kwak ,  Soon-Moon Jung ,  Sung-Bong Kim

IPC分类号： G11C506

CPC分类号： G11C5/063 ,  G11C11/412

摘要： A semiconductor memory device is disclosed. The device is comprised of a plurality of word lines; a plurality of bit lines arranged in perpendicular to the word lines. In addition, a plurality of supply voltage lines extend in the same direction as the bit lines. Also, a plurality of first ground voltage lines are arranged in the same direction as the bit lines. Further, a plurality of second ground voltage lines are arranged in the same direction as the word lines. A plurality of memory cells are each connected between one of the word lines and one of the bit lines. Here, the ground voltage lines are arranged in a matrix shape to reduce the resistance of the ground voltage line and secure the margin between the supply voltage level and the ground voltage level of the data latched by the memory cells to thereby prevent an operational failure of the device.

摘要翻译： 公开了一种半导体存储器件。 该装置由多条字线组成; 垂直于字线布置的多个位线。 此外，多个电源电压线沿与位线相同的方向延伸。 此外，多个第一接地电压线被布置在与位线相同的方向上。 此外，多个第二接地电压线布置在与字线相同的方向上。 多个存储单元分别连接在一条字线和一条位线之间。 这里，接地电压线被布置成矩阵形状以减小接地电压线的电阻并且确保由存储器单元锁存的数据的电源电压电平和接地电压电平之间的裕度，从而防止 装置。