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    Double consecutive error correction
    52.
    发明授权
    Double consecutive error correction 有权

    公开(公告)号：US09748977B2

    公开(公告)日：2017-08-29

    申请号：US15355199

    申请日：2016-11-18

    Applicant: INTEL CORPORATION

    Inventor： Alexander Gendler ,  Gilad Cohen

    IPC: H03M13/00 ,  H03M13/29 ,  G06F11/10 ,  H03M13/13

    CPC classification number: H03M13/2906 ,  G06F11/1008 ,  H03M13/13 ,  H03M13/616

    Abstract: Described is a processor with a data storage structure operative to store data and a first error correction code that corresponds to the data. The processor further includes circuitry to compare the first and second error correction codes to obtain a comparison result. There are no errors in the data when the comparison result is equal to zero and there is at least one error in the data when the comparison result is not equal to zero. The circuitry corrects a single bit error of the data when the comparison result matches one of the unique combination of bit values of one of the plurality of bit groups in the generator matrix and corrects two consecutive data bits of the data when the comparison result corresponds to a predefined number of values as a result of an exclusive-or (XOR) operation performed on two consecutive bit groups of the generator matrix.

    TEMPORARY TRANSFER OF A MULTITHREADED IP CORE TO SINGLE OR REDUCED THREAD CONFIGURATION DURING THREAD OFFLOAD TO CO-PROCESSOR
    54.
    发明申请
    TEMPORARY TRANSFER OF A MULTITHREADED IP CORE TO SINGLE OR REDUCED THREAD CONFIGURATION DURING THREAD OFFLOAD TO CO-PROCESSOR 审中-公开
    将多路复用IP核的临时转移单向或减少螺纹配置在螺纹卸载过程中与CO加工器

    公开(公告)号：US20160170767A1

    公开(公告)日：2016-06-16

    申请号：US14568453

    申请日：2014-12-12

    Applicant: Intel Corporation

    Inventor： Alexander Gendler

    IPC: G06F9/38 ,  G06F9/30

    CPC classification number: G06F9/3851

    Abstract: In one embodiment, a multithreading processor cores may be offload threads to one or more coprocessors. When a thread executing on a simultaneous multithreading processor core is offloaded to a coprocessor, the processor core may temporarily switch to an opportunistic single threaded mode in which all processor resources are dedicated to processing a single thread. In one embodiment an opportunistic reduced thread mode is enabled in which a processor core is reconfigured to provide processor resources previously reserved for one or more offloaded threads to the remaining threads executing on the processor.

    Abstract translation: 在一个实施例中，多线程处理器核可以将线程卸载到一个或多个协处理器。 当在同时多线程处理器核上执行的线程被卸载到协处理器时，处理器核心可能暂时切换到机会性单线程模式，其中所有处理器资源专用于处理单个线程。 在一个实施例中，允许机会主义缩减线程模式，其中处理器核心被重新配置以将先前为一个或多个卸载线程预留的处理器资源提供给在处理器上执行的剩余线程。

    Reduced power mode of a cache unit
    55.
    发明授权
    Reduced power mode of a cache unit 有权
    降低高速缓存单元的功率模式

    公开(公告)号：US09360924B2

    公开(公告)日：2016-06-07

    申请号：US13904055

    申请日：2013-05-29

    Applicant: Intel Corporation

    Inventor： Alexander Gendler ,  Larisa Novakovsky ,  Ariel Sabba ,  Niv Tokman

    IPC: G06F1/26 ,  G06F1/32 ,  G06F12/08

    CPC classification number: G06F1/3275 ,  G06F1/3206 ,  G06F12/0811 ,  G06F2201/885 ,  Y02D10/14

    Abstract: In an embodiment, a processor includes a plurality of cores and a cache unit reserved for a first core of the plurality of cores. The cache unit may include a first cache slice, a second cache slice, and power logic to switch operation of the cache unit between a first operating mode and a second operating mode. The first operating mode may include use of both the first cache slice and the second cache slice. The second operating mode may include use of the first cache slice and disabling the second cache slice. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，处理器包括多个核心和为多个核心中的第一核心预留的高速缓存单元。 高速缓存单元可以包括第一高速缓存片，第二高速缓存片和用于在第一操作模式和第二操作模式之间切换高速缓存单元的操作的电源逻辑。 第一操作模式可以包括使用第一高速缓存片和第二高速缓存片。 第二操作模式可以包括使用第一高速缓存片并禁用第二高速缓存片。 描述和要求保护其他实施例。

    Apparatus and Method to Provide Multiple Domain Clock Frequencies In A Processor
    56.
    发明申请
    Apparatus and Method to Provide Multiple Domain Clock Frequencies In A Processor 有权
    在处理器中提供多个域时钟频率的装置和方法

    公开(公告)号：US20160147249A1

    公开(公告)日：2016-05-26

    申请号：US14551310

    申请日：2014-11-24

    Applicant: Intel Corporation

    Inventor： Alexander Gendler

    IPC: G06F1/06 ,  G06F1/10

    CPC classification number: G06F1/3296 ,  G06F1/04 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/172

    Abstract: In an embodiment, a processor includes at least one core, a first domain to operate at a first clock frequency, and a second domain to operate at a second clock frequency that is lower than the first clock frequency. The processor also includes phase locked loop (PLL) logic to generate a first signal having a first frequency corresponding to the first clock frequency and to provide the first signal to the first domain. The processor also includes a first clock to produce a first squash signal that is determined based at least in part on the second clock frequency, and also first logic to generate a second signal having a second frequency corresponding to the second clock frequency by gating the first signal with the first squash signal and to provide the second signal to the second domain. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，处理器包括至少一个核心，以第一时钟频率工作的第一域和第二域，以在低于第一时钟频率的第二时钟频率下工作。 处理器还包括锁相环（PLL）逻辑，以产生具有对应于第一时钟频率的第一频率的第一信号，并将第一信号提供给第一域。 处理器还包括第一时钟以产生至少部分地基于第二时钟频率确定的第一南瓜信号，并且还包括第一逻辑，以通过门控第一时钟频率产生具有对应于第二时钟频率的第二频率的第二信号 信号与第一南瓜信号并向第二域提供第二信号。 描述和要求保护其他实施例。

    Processor core energy management
    59.
    发明授权
    Processor core energy management 有权

    公开(公告)号：US11360540B2

    公开(公告)日：2022-06-14

    申请号：US16261370

    申请日：2019-01-29

    Applicant: Intel Corporation

    Inventor： Alexander Gendler

    IPC: G06F1/00 ,  G06F1/324 ,  G06F1/3206 ,  G06F1/3296

    Abstract: Methods and apparatus relating to techniques for processor core energy management are described. In an embodiment, energy management logic causes a modification to energy consumption by an electrical load (such as a processor core) based at least in part on comparison of an electrical current value and an operating current threshold value. The electrical current value is detected at an electrical current sensor coupled to the electrical load. Other embodiments are also disclosed and claimed.

    Fast dynamic capacitance, frequency, and/or voltage throttling apparatus and method
    60.
    发明授权
    Fast dynamic capacitance, frequency, and/or voltage throttling apparatus and method 有权

    公开(公告)号：US11275663B2

    公开(公告)日：2022-03-15

    申请号：US16896070

    申请日：2020-06-08

    Applicant: Intel Corporation

    Inventor： Alexander Gendler ,  Nimrod Angel ,  Ameya Ambardekar ,  Sapumal Wijeratne ,  Vikas Vij ,  Tod Schiff ,  Alexander Uan-Zo-Li

    IPC: G06F1/3296 ,  G06F11/30 ,  G06F11/07 ,  G06F9/30 ,  G06F9/4401

    Abstract: A dedicated pin of a processor or system-on-chip (SoC) is used to indicate whether power level (e.g., charge, voltage, and/or current) of a battery falls below a threshold. The threshold can be predetermined or programmable. The battery is used to provide power to the processor and/or SoC. Upon determining that the power level of the battery falls below the threshold, the processor by-passes the conventional process of entering low performance or power mode, and directly throttles voltage and/or operating frequency of the processor. This allows the processor to continue to operate at low battery power. The fast transition (e.g., approximately 10 μS) from an active state to a low performance or power mode, in accordance with a logic level of the voltage on the dedicated pin, reduces decoupling capacitor design requirements, and makes it possible for the processor to adapt higher package power control settings (e.g., PL4).

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