公开(公告)号：US20160254036A1

公开(公告)日：2016-09-01

申请号：US14926860

申请日：2015-10-29

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  John B. Halbert

IPC: G11C7/10 ,  G06F13/42

CPC classification number: G06F3/0659 ,  G06F3/0605 ,  G06F3/0683 ,  G06F13/4022 ,  G06F13/4282 ,  G06F13/4295 ,  G06F15/7807 ,  G11C7/1003 ,  G11C7/1021 ,  G11C7/1072 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4097 ,  Y02D10/14 ,  Y02D10/151

Abstract: Flexible command addressing for memory. An embodiment of a memory device includes a dynamic random-access memory (DRAM); and a system element coupled with the DRAM, the system element including a memory controller for control of the DRAM. The DRAM includes a memory bank, a bus, the bus including a plurality of pins for the receipt of commands, and a logic, wherein the logic provides for shared operation of the bus for a first type of command and a second type of command received on a first set of pins.

Abstract translation: 内存灵活的命令寻址。 存储器件的实施例包括动态随机存取存储器（DRAM）; 以及与DRAM耦合的系统元件，所述系统元件包括用于控制DRAM的存储器控​​制器。 DRAM包括存储体，总线，总线包括用于接收命令的多个引脚和逻辑，其中逻辑提供用于第一类型的命令的总线的共享操作和接收的第二类型的命令 在第一组引脚上。

公开(公告)号：US09299400B2

公开(公告)日：2016-03-29

申请号：US13631781

申请日：2012-09-28

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  John B. Halbert

IPC: G11C13/00 ,  G11C7/10 ,  G11C11/406 ,  G11C11/4078

CPC classification number: G11C7/1072 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/4078

Abstract: A memory controller issues a targeted refresh command in response to detection by a distributed detector. A memory device includes detection logic that monitors for a row hammer event, which is a threshold number of accesses to a row within a time threshold that can cause data corruption to a physically adjacent row (a “victim” row). The memory device sends an indication of the row hammer event to the memory controller. In response to the row hammer event indication, the memory controller sends one or more commands to the memory device to cause the memory device to perform a targeted refresh that will refresh the victim row.

Abstract translation: 存储器控制器响应于分布式检测器的检测器发出目标刷新命令。 存储器装置包括检测逻辑，该检测逻辑监视行敲击事件，该行敲击事件是对时间阈值内可能导致数据损坏到物理相邻行（“受害者”行）的行的阈值数量。 存储器件向存储器控制器发送行锤事件的指示。 响应于行锤事件指示，存储器控制器将一个或多个命令发送到存储器设备，以使存储器设备执行将刷新受害者行的目标刷新。

公开(公告)号：US09152257B2

公开(公告)日：2015-10-06

申请号：US13730642

申请日：2012-12-28

Applicant: Intel Corporation

Inventor： James A. McCall ,  Kuljit S. Bains ,  Derek M. Conrow ,  Aaron Martin

IPC: H03K3/012 ,  G06F3/041 ,  H03K19/00 ,  H03K19/0175

CPC classification number: H03K19/0008 ,  G06F3/041 ,  G06F3/0412 ,  H03K19/0005 ,  H03K19/017509 ,  H03K19/017545

Abstract: An output driver includes control logic configured to switch on a pull-up circuit and a pull-down circuit to provide an output impedance for a logic low on a transmission line. The output driver includes a variable pull-up resistor. The control logic is configured to switch on the pull-up circuit to a first value of impedance to drive a logic high on the transmission line. The control logic is configured to switch on the pull-up circuit to a second value of impedance and to switch on the pull-down circuit to provide the output impedance to drive a logic low on the transmission line. The system could alternatively be configured for the inverse to switch on a combination of pull-up and pull-down circuits for a logic high, where the pull-down circuit is switched on for a logic low.

Abstract translation: 输出驱动器包括被配置为接通上拉电路和下拉电路以提供传输线路上的逻辑低电平的输出阻抗的控制逻辑。 输出驱动器包括一个可变上拉电阻。 控制逻辑被配置为将上拉电路接通到第一阻抗值，以驱动传输线上的逻辑高电平。 控制逻辑被配置为将上拉电路接通到第二阻抗值，并且接通下拉电路以提供输出阻抗以驱动传输线上的逻辑低电平。 可替代地，该系统可以被配置为用于将逻辑高的上拉电路和下拉电路的组合打开，其中下拉电路被接通为逻辑低电平。

公开(公告)号：US12210456B2

公开(公告)日：2025-01-28

申请号：US17214749

申请日：2021-03-26

Applicant: Intel Corporation

Inventor： Kuljit S. Bains

IPC: G06F12/0862 ,  G06F12/0879 ,  G06F12/0882 ,  G06F13/16

Abstract: A memory is described. The memory includes row buffer circuitry to store a page. The page is divided into sections, wherein, at least one of the sections of the page is to be sequestered for the storage of meta data, and wherein, a first subset of column address bits is to: 1) define a particular section of the page, other than the at least one sequestered sections of the page, whose data is targeted by a burst access; and, 2) define a field within the at least one of the sequestered sections of the page that stores meta data for the particular section.

公开(公告)号：US11989106B2

公开(公告)日：2024-05-21

申请号：US16711243

申请日：2019-12-11

Applicant: Intel Corporation

Inventor： Jongwon Lee ,  Kuljit S. Bains

IPC: G06F11/20 ,  G06F12/0875 ,  G06F12/10 ,  G11C11/4091 ,  G11C29/44 ,  G11C11/408

CPC classification number: G06F11/2094 ,  G06F12/0875 ,  G06F12/10 ,  G11C11/4091 ,  G11C29/4401 ,  G06F2201/82 ,  G06F2212/45 ,  G11C11/4085

Abstract: In a memory system, a memory device has a memory array with multiple rows of memory having logical addresses mapped to their physical addresses and at least one spare row not having a logical address mapped to its physical address. A controller detects a failure of one of the multiple rows of memory (“failure row”) and executes a post package repair (PPR) mode. The controller can be internal to the memory device or external to the memory device. The memory device includes an internal scratchpad to allow transfer of data contents from the failure row to the spare row. The controller can map the logical address of the failure row from the physical address of the failure row to the physical address of the spare row, transfer data contents from the failure row to the internal scratchpad, and transfer the data contents from the internal scratchpad to the spare row.

公开(公告)号：US11144466B2

公开(公告)日：2021-10-12

申请号：US16433663

申请日：2019-06-06

Applicant: Intel Corporation

Inventor： Jongwon Lee ,  Vivek Kozhikkottu ,  Kuljit S. Bains ,  Hussein Alameer

IPC: G06F12/0882 ,  G11C7/10

Abstract: An embodiment of a memory device includes technology for a memory cell array logically organized in two or more banks of at least two rows and two columns per bank, and two or more local caches respectively coupled to the two or more banks of the memory cell array, where each local cache has a size which is an integer multiple of a memory page size of the memory cell array. Other embodiments are disclosed and claimed.

公开(公告)号：US10802532B2

公开(公告)日：2020-10-13

申请号：US16429872

申请日：2019-06-03

Applicant: Intel Corporation

Inventor： George Vergis ,  Kuljit S. Bains ,  Bill Nale

IPC: G06F1/06 ,  G06F13/42 ,  G11C7/10 ,  G11C5/04 ,  H01L23/00 ,  G11C5/06 ,  G06F3/06 ,  G06F12/00

Abstract: Examples include techniques to mirror a command/address or interpret command/address logic at a memory device. A memory device located on a dual in-line memory module (DIMM) may include circuitry having logic capable of receiving a command/address signal and mirror a command/address or interpret command/address logic indicated in the command/address signal based on one or more strap pins for the memory device.

公开(公告)号：US10592445B2

公开(公告)日：2020-03-17

申请号：US16208224

申请日：2018-12-03

Applicant: Intel Corporation

Inventor： Bill Nale ,  Christopher E. Cox ,  Kuljit S. Bains ,  George Vergis ,  James A. McCall ,  Chong J. Zhao ,  Suneeta Sah ,  Pete D. Vogt ,  John R. Goles

IPC: G06F11/16 ,  G06F13/16 ,  G11C11/4096 ,  G06F13/40 ,  G11C14/00 ,  G11C5/04 ,  G11C7/10

Abstract: Examples include techniques to access or operate a dual in-line memory module (DIMM) via one or multiple data channels. In some examples, memory devices at or on the DIMM may be accessed via one or more data channels. The one or more data channels arranged such that the DIMM is configured to operate in a dual channel mode that includes two data channels or to operate in a single channel mode that includes a single data channel.

公开(公告)号：US10522207B2

公开(公告)日：2019-12-31

申请号：US15665143

申请日：2017-07-31

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  Shay Fux ,  John B. Halbert

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/4074

Abstract: Embodiments are generally directed to performance of additional refresh operations during self-refresh mode. An embodiment of a memory device includes one or more memory banks, a mode register set, the mode register set including a first set of mode register bits, and a control logic to provide control operations for the memory device, the operations including refresh operations for the one or more memory banks in a refresh credit mode. The control logic is to perform one or more extra refresh cycles in response to receipt of a self-refresh command, the self-refresh command to provide current refresh status information, and is to store information in the first set of mode register bits regarding a modified refresh status after the performance of the one or more extra refresh cycles.

公开(公告)号：US20190286566A1

公开(公告)日：2019-09-19

申请号：US16433663

申请日：2019-06-06

Applicant: Intel Corporation

Inventor： Jongwon Lee ,  Vivek Kozhikkottu ,  Kuljit S. Bains ,  Hussein Alameer

IPC: G06F12/0882 ,  G11C7/10

Abstract: An embodiment of a memory device includes technology for a memory cell array logically organized in two or more banks of at least two rows and two columns per bank, and two or more local caches respectively coupled to the two or more banks of the memory cell array, where each local cache has a size which is an integer multiple of a memory page size of the memory cell array. Other embodiments are disclosed and claimed.