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公开(公告)号：US10338957B2
公开(公告)日：2019-07-02
申请号：US15391208
申请日：2016-12-27
Applicant: Intel Corporation
Inventor： Vincent R. Scarlata , Carlos V. Rozas , Simon P. Johnson , Francis X. McKeen , Mona Vij , Somnath Chakrabarti , Brandon Baker , Ittai Anati , Ilya Alexandrovich
Abstract: A secure migration enclave is provided to identify a launch of a particular virtual machine on a host computing system, where the particular virtual machine is launched to include a secure quoting enclave to perform an attestation of one or more aspects of the virtual machine. A root key for the particular virtual machine is generated using the secure migration enclave hosted on the host computing system for use in association with provisioning the secure quoting enclave with an attestation key to be used in the attestation. The migration enclave registers the root key with a virtual machine registration service.
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公开(公告)号：US10282306B2
公开(公告)日：2019-05-07
申请号：US15861364
申请日：2018-01-03
Applicant: INTEL CORPORATION
Inventor： Krystof C. Zmudzinski , Siddhartha Chhabra , Uday R. Savagaonkar , Simon P. Johnson , Rebekah M. Leslie-Hurd , Francis X. McKeen , Gilbert Neiger , Raghunandan Makaram , Carlos V. Rozas , Amy L. Santoni , Vincent R. Scarlata , Vedvyas Shanbhogue , Ilya Alexandrovich , Ittai Anati , Wesley H. Smith , Michael Goldsmith
IPC: G06F12/14 , G06F9/455 , G06F12/109 , G06F12/1009 , G06F12/1027 , G06F12/1036 , G06F12/1045
Abstract: A processor for supporting secure memory intent is disclosed. The processor of the disclosure includes a memory execution unit to access memory and a processor core coupled to the memory execution unit. The processor core is to receive a request to access a convertible page of the memory. In response to the request, the processor core to determine an intent for the convertible page in view of a page table entry (PTE) corresponding to the convertible page. The intent indicates whether the convertible page is to be accessed as at least one of a secure page or a non-secure page.
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公开(公告)号：US20180365438A1
公开(公告)日：2018-12-20
申请号：US15946401
申请日：2018-04-05
Applicant: Intel Corporation
Inventor： Binata Bhattacharyya , Raghunandan Makaram , Amy L. Santoni , George Z. Chrysos , Simon P. Johnson , Brian S. Morris , Francis X. McKeen
CPC classification number: G06F21/62 , G06F12/1441 , G06F21/602 , G06F21/64 , G06F21/74 , G06F21/78 , G06F2221/2113
Abstract: A processor implementing techniques for supporting configurable security levels for memory address ranges is disclosed. In one embodiment, the processor includes a processing core a memory controller, operatively coupled to the processing core, to access data in an off-chip memory and a memory encryption engine (MEE) operatively coupled to the memory controller. The MEE is to responsive to detecting a memory access operation with respect to a memory location identified by a memory address within a memory address range associated with the off-chip memory, identify a security level indicator associated with the memory location based on a value stored on a security range register. The MEE is further to access at least a portion of a data item associated with the memory address range of the off-chip memory in view of the security level indicator.
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公开(公告)号：US20180239713A1
公开(公告)日：2018-08-23
申请号：US15861364
申请日：2018-01-03
Applicant: INTEL CORPORATION
Inventor： Krystof C. Zmudzinski , Siddhartha Chhabra , Uday R. Savagaonkar , Simon P. Johnson , Rebekah M. Leslie-Hurd , Francis X. McKeen , Gilbert Neiger , Raghunandan Makaram , Carlos V. Rozas , Amy L. Santoni , Vincent R. Scarlata , Vedvyas Shanbhogue , Ilya Alexandrovich , Ittai Anati , Wesley H. Smith , Michael Goldsmith
IPC: G06F12/1009 , G06F12/1027 , G06F9/455 , G06F12/14 , G06F12/109
CPC classification number: G06F12/1009 , G06F9/455 , G06F9/45558 , G06F12/1027 , G06F12/1036 , G06F12/1045 , G06F12/109 , G06F12/1441 , G06F2009/45583 , G06F2212/1016 , G06F2212/1052 , G06F2212/151 , G06F2212/657 , G06F2212/684
Abstract: A processor for supporting secure memory intent is disclosed. The processor of the disclosure includes a memory execution unit to access memory and a processor core coupled to the memory execution unit. The processor core is to receive a request to access a convertible page of the memory. In response to the request, the processor core to determine an intent for the convertible page in view of a page table entry (PTE) corresponding to the convertible page. The intent indicates whether the convertible page is to be accessed as at least one of a secure page or a non-secure page.
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公开(公告)号：US09959418B2
公开(公告)日：2018-05-01
申请号：US14803956
申请日：2015-07-20
Applicant: Intel Corporation
Inventor： Binata Bhattacharyya , Raghunandan Makaram , Amy L. Santoni , George Z. Chrysos , Simon P. Johnson , Brian S. Morris , Francis X. McKeen
CPC classification number: G06F21/62 , G06F21/602 , G06F21/64 , G06F21/78 , G06F2221/2113
Abstract: A processor implementing techniques for supporting configurable security levels for memory address ranges is disclosed. In one embodiment, the processor includes a processing core a memory controller, operatively coupled to the processing core, to access data in an off-chip memory and a memory encryption engine (MEE) operatively coupled to the memory controller. The MEE is to responsive to detecting a memory access operation with respect to a memory location identified by a memory address within a memory address range associated with the off-chip memory, identify a security level indicator associated with the memory location based on a value stored on a security range register. The MEE is further to access at least a portion of a data item associated with the memory address range of the off-chip memory in view of the security level indicator.
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Patent Agency Ranking
公开(公告)号：US09875189B2
公开(公告)日：2018-01-23
申请号：US14738037
申请日：2015-06-12
Applicant: INTEL CORPORATION
Inventor： Krystof C. Zmudzinski , Siddhartha Chhabra , Uday R. Savagaonkar , Simon P. Johnson , Rebekah M. Leslie-Hurd , Francis X. McKeen , Gilbert Neiger , Raghunandan Makaram , Carlos V. Rozas , Amy L. Santoni , Vincent R. Scarlata , Vedvyas Shanbhogue , Ilya Alexandrovich , Ittai Anati , Wesley H. Smith , Michael Goldsmith
IPC: G06F12/00 , G06F13/00 , G06F13/28 , G06F12/1009 , G06F12/1027 , G06F12/1036 , G06F12/109 , G06F12/14 , G06F9/455 , G06F12/1045
CPC classification number: G06F12/1009 , G06F9/455 , G06F9/45558 , G06F12/1027 , G06F12/1036 , G06F12/1045 , G06F12/109 , G06F12/1441 , G06F2009/45583 , G06F2212/1016 , G06F2212/1052 , G06F2212/151 , G06F2212/657 , G06F2212/684
Abstract: A processor for supporting secure memory intent is disclosed. The processor of the disclosure includes a memory execution unit to access memory and a processor core coupled to the memory execution unit. The processor core is to receive a request to access a convertible page of the memory. In response to the request, the processor core to determine an intent for the convertible page in view of a page table entry (PTE) corresponding to the convertible page. The intent indicates whether the convertible page is to be accessed as at least one of a secure page or a non-secure page.
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公开(公告)号：US20180011793A1
公开(公告)日：2018-01-11
申请号：US15711615
申请日：2017-09-21
Applicant: Intel Corporation
Inventor： Rebekah M. Leslie-Hurd , Carlos V. Rozas , Francis X. Mckeen , Ilya Alexandrovich , Vedvyas Shanbhogue , Bin Xing , Mark W. Shanahan , Simon P. Johnson
IPC: G06F12/0844 , G06F12/0882
CPC classification number: G06F12/0844 , G06F11/073 , G06F11/0775 , G06F12/0882 , G06F2212/1032 , G06F2212/1052 , G06F2212/281 , G06F2212/312 , G06F2212/402 , G06F2212/608
Abstract: A processor implementing techniques to supporting fault information delivery is disclosed. In one embodiment, the processor includes a memory controller unit to access an enclave page cache (EPC) and a processor core coupled to the memory controller unit. The processor core to detect a fault associated with accessing the EPC and generate an error code associated with the fault. The error code reflects an EPC-related fault cause. The processor core is further to encode the error code into a data structure associated with the processor core. The data structure is for monitoring a hardware state related to the processor core.
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公开(公告)号：US20180006809A1
公开(公告)日：2018-01-04
申请号：US15200604
申请日：2016-07-01
Applicant: Intel Corporation
Inventor： Vincent R. Scarlata , Francis X. McKeen , Carlos V. Rozas , Simon P. Johnson , Bo Zhang , Mona Vij , Brandon Baker , Mohan J. Kumar , Asit K. Mallick , Mark A. Gentry , Somnath Chakrabarti
CPC classification number: H04L9/0816 , G06F21/6218 , H04L9/0861 , H04L9/088 , H04L9/0894 , H04L9/14 , H04L63/06
Abstract: Particular embodiments described herein provide for an electronic device that can be configured to store data in a secure domain in a cloud network, create encryption keys, where each encryption key is to provide a different type of access to the data, and store the encryption keys in a secure domain key store in the cloud network. In an example, each encryption key provides access to a different version of the data. In another example, a counter engine stores the location of each version of the data in the cloud network.
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公开(公告)号：US09766889B2
公开(公告)日：2017-09-19
申请号：US15074573
申请日：2016-03-18
Applicant: Intel Corporation
Inventor： Rebekah Leslie-Hurd , Carlos V. Rozas , Vincent R. Scarlata , Simon P. Johnson , Uday R. Savagaonkar , Barry E. Huntley , Vedvyas Shanbhogue , Ittai Anati , Francis X. Mckeen , Michael A. Goldsmith , Ilya Alexandrovich , Alex Berenzon , Wesley H. Smith , Gilbert Neiger
IPC: G06F12/00 , G06F9/30 , G06F12/0875 , G06F9/44 , G06F12/084 , G06F12/14
CPC classification number: G06F9/3004 , G06F9/30047 , G06F9/30076 , G06F9/44 , G06F12/084 , G06F12/0875 , G06F12/1483 , G06F2212/452
Abstract: Embodiments of an invention for memory management in secure enclaves are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive a first instruction and a second instruction. The execution unit is to execute the first instruction, wherein execution of the first instruction includes allocating a page in an enclave page cache to a secure enclave. The execution unit is also to execute the second instruction, wherein execution of the second instruction includes confirming the allocation of the page.
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公开(公告)号：US20170109315A1
公开(公告)日：2017-04-20
申请号：US15393153
申请日：2016-12-28
Applicant: Intel Corporation
Inventor： Robert J. Safranek , Robert G. Blankenship , Venkatraman Iyer , Jeff Willey , Robert H. Beers , Darren S. Jue , Arvind A. Kumar , Debendra Das Sharma , Jeffrey C. Swanson , Bahaa Fahim , Vedaraman Geetha , Aaron T. Spink , Fulvio Spagna , Rahul R. Shah , Sitaraman V. Iyer , William Harry Nale , Abhishek Das , Simon P. Johnson , Yuvraj S. Dhillon , Yen-Cheng Liu , Raj K. Ramanujan , Robert A. Maddox , Herbert H. Hum , Ashish Gupta
CPC classification number: G06F13/22 , G06F1/3287 , G06F8/71 , G06F8/73 , G06F8/77 , G06F9/30145 , G06F9/44505 , G06F9/466 , G06F11/1004 , G06F12/0806 , G06F12/0808 , G06F12/0813 , G06F12/0815 , G06F12/0831 , G06F12/0833 , G06F13/4022 , G06F13/4068 , G06F13/4221 , G06F13/4273 , G06F13/4282 , G06F13/4286 , G06F13/4291 , G06F2212/1016 , G06F2212/2542 , G06F2212/622 , H04L9/0662 , H04L12/4641 , H04L45/74 , H04L49/15 , Y02D10/13 , Y02D10/14 , Y02D10/151 , Y02D10/40 , Y02D10/44 , Y02D30/30
Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.
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