公开(公告)号：US10088518B1

公开(公告)日：2018-10-02

申请号：US15474674

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Mayue Xie ,  Zhiguo Qian ,  Jong-Ru Guo ,  Zhichao Zhang ,  Zuoguo Wu

IPC: G01R31/08 ,  G01R31/28

Abstract: A die with a transmission circuit, a reception circuit, and a comparison circuit can be provided. The transmission circuit can be configured to transmit a first signal through a first channel at a first transmission rate and a first transmission amplitude. The reception circuit can be in communication with the transmission circuit through the first channel. The reception circuit can receive a second signal at a first reception rate and at a first reception amplitude. The comparison circuit can be in communication with the transmission circuit and the reception circuit. The comparison circuit can be configured to: determine a first rate error value, determine a first amplitude error value, compare the first rate error value with a rate threshold to determine a first rate error occurrence, and compare the first amplitude error value with an amplitude threshold to determine a first amplitude error occurrence.

公开(公告)号：US20180191374A1

公开(公告)日：2018-07-05

申请号：US15851747

申请日：2017-12-22

Applicant: Intel Corporation

Inventor： Zuoguo Wu ,  Debendra Das Sharma ,  Md. Mohiuddin Mazumder ,  Subas Bastola ,  Kai Xiao

IPC: H03M13/11 ,  G06F13/40 ,  G06F13/36 ,  G06F13/42

CPC classification number: H03M13/11 ,  G06F13/36 ,  G06F13/385 ,  G06F13/4068 ,  G06F13/4282 ,  G06F2213/0026

Abstract: An identification is made that a link is to exit an active state, the link comprising a plurality of lanes. Parity information is maintained for the lanes based on data previously sent over the link, and an indication of the parity information is sent prior to the exit from the active state.

公开(公告)号：US09946676B2

公开(公告)日：2018-04-17

申请号：US14669975

申请日：2015-03-26

Applicant: Intel Corporation

Inventor： Mahesh Wagh ,  Zuoguo Wu ,  Venkatraman Iyer ,  Gerald S. Pasdast ,  Mark S. Birrittella ,  Ishwar Agarwal ,  Lip Khoon Teh ,  Su Wei Lim ,  Anoop Kumar Upadhyay

IPC: G06F17/50 ,  G06F13/40 ,  G06F13/36

CPC classification number: G06F13/4022 ,  G06F13/36 ,  G06F13/4068

Abstract: A system-on-a-chip, such as a logical PHY, may be divided into hard IP blocks with fixed routing, and soft IP blocks with flexible routing. Each hard IP block may provide a fixed number of lanes. Using p hard IP blocks, where each block provides n data lanes, h=n*p total hard IP data lanes are provided. Where the system design calls for k total data lanes, it is possible that k≠h, so that ┌k/n┐ hard IP blocks provide h=n*p available hard IP data lanes. In that case, h−k lanes may be disabled. In cases where lane reversals occur, such as between hard IP and soft IP, bowtie routing may be avoided by the use of a multiplexer-like programmable switch within the soft IP.

公开(公告)号：US20240311330A1

公开(公告)日：2024-09-19

申请号：US18399463

申请日：2023-12-28

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Narasimha Lanka ,  Peter Onufryk ,  Swadesh Choudhary ,  Gerald Pasdast ,  Zuoguo Wu ,  Dimitrios Ziakas ,  Sridhar Muthrasanallur

IPC: G06F13/42 ,  G06F13/16

CPC classification number: G06F13/4295 ,  G06F13/1689 ,  G06F2213/0038 ,  G06F2213/0064

Abstract: Embodiments described herein may include apparatus, systems, techniques, or processes that are directed to on-package die-to-die (D2D) interconnects. Specifically, embodiments herein may relate to on-package D2D interconnects for memory that use or relate to the Universal Chiplet Interconnect Express (UCIe) adapter or physical layer (PHY). Other embodiments are described and claimed.

公开(公告)号：US11632130B2

公开(公告)日：2023-04-18

申请号：US17681364

申请日：2022-02-25

Applicant: Intel Corporation

Inventor： Zuoguo Wu ,  Debendra Das Sharma ,  Md. Mohiuddin Mazumder ,  Subas Bastola ,  Kai Xiao

IPC: H03M13/11 ,  G06F13/38 ,  G06F13/36 ,  G06F13/40 ,  G06F13/42

Abstract: An identification is made that a link is to exit an active state, the link comprising a plurality of lanes. Parity information is maintained for the lanes based on data previously sent over the link, and an indication of the parity information is sent prior to the exit from the active state.

公开(公告)号：US20220350698A1

公开(公告)日：2022-11-03

申请号：US17721290

申请日：2022-04-14

Applicant: Intel Corporation

Inventor： Venkatraman Iyer ,  Robert G. Blankenship ,  Mahesh Wagh ,  Zuoguo Wu

IPC: G06F11/10 ,  H04L1/00 ,  H04L1/20 ,  H04L9/40 ,  G06F13/16

Abstract: First data is received on a plurality of data lanes of a physical link and a stream signal corresponding to the first data is received on a stream lane identifying a type of the first data. A first instance of an error detection code of a particular type is identified in the first data. Second data is received on at least a portion of the plurality of data lanes and a stream signal corresponding to the second data is received on the stream lane identifying a type of the second data. A second instance of the error detection code of the particular type is identified in the second data. The stream lane is another one of the lanes of the physical link and, in some instance, the type of the second data is different from the type of the first data.

公开(公告)号：US11386033B2

公开(公告)日：2022-07-12

申请号：US17121534

申请日：2020-12-14

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Zuoguo Wu ,  Mahesh Wagh ,  Mohiuddin M. Mazumder ,  Venkatraman Iyer ,  Jeff C. Morriss

IPC: G06F13/40 ,  H01L25/065 ,  G06F13/42 ,  H01L23/538

Abstract: An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.

公开(公告)号：US20210320722A1

公开(公告)日：2021-10-14

申请号：US17304556

申请日：2021-06-23

Applicant: Intel Corporation

Inventor： Zuoguo Wu ,  Ling Liao ,  David Hui

IPC: H04B10/50 ,  H04B10/61 ,  H04B10/40

Abstract: In one embodiment, an apparatus includes a processor, a laser, and a modulator. The processor is to generate a first electrical signal including first data and a second electrical signal including second data. The laser is to generate a multiplexed carrier signal comprising a first carrier signal and a second carrier signal, the laser to operate at a first laser power setting. The modulator is to generate a multiplexed optical signal including a first optical signal based in part on the first electrical signal and the first carrier signal and a second optical signal based in part on the second electrical signal and the second carrier signal. The apparatus is to transmit the multiplexed optical signal to a device and to retransmit the first data from the apparatus to the device based on a detection of error in a received version of the first data at the device. Other embodiments are described and claimed.

公开(公告)号：US20210311120A1

公开(公告)日：2021-10-07

申请号：US17353453

申请日：2021-06-21

Applicant: Intel Corporation

Inventor： Jong-Ru Guo ,  Jingbo Li ,  Xiaoning Ye ,  Zuoguo Wu ,  Howard L. Heck

IPC: G01R31/317 ,  H04L25/02

Abstract: An apparatus may comprise a skew detection circuit to sample a common mode voltage of a differential signal, wherein the sampled common mode voltage is indicative of an amount of skew between a first signal of the differential signal and a second signal of the differential signal; and a skew compensation circuit to adjust a delay of the first signal or the second signal based on the sampled common mode voltage to reduce the amount of skew.

公开(公告)号：US10965047B2

公开(公告)日：2021-03-30

申请号：US16431498

申请日：2019-06-04

Applicant: Intel Corporation

Inventor： Jong-Ru Guo ,  Yunhui Chu ,  Jun Liao ,  Kai Xiao ,  Jingbo Li ,  Yuanhong Zhao ,  Mo Liu ,  Beomtaek Lee ,  James A. McCall ,  Jaejin Lee ,  Xiaoning Ye ,  Zuoguo Wu ,  Xiang Li

IPC: H05K7/00 ,  H01R12/71 ,  H01R13/66 ,  H01R103/00

Abstract: Embodiments may relate to a connector. The connector may include a plurality of connector pins that are to communicatively couple an element of a printed circuit board (PCB) with an element of an electronic device when the element of the PCB and the element of the electronic device are coupled with the connector. The connector may also include an active circuit that is communicatively coupled with a pin of the plurality of pins. The active circuit may be configured to match an impedance of the element of the PCB with an impedance of the element of the electronic device. Other embodiments may be described or claimed.