公开(公告)号：US10103145B1

公开(公告)日：2018-10-16

申请号：US15799286

申请日：2017-10-31

Applicant: International Business Machines Corporation

Inventor： Sami Rosenblatt ,  Rasit O. Topaloglu

IPC: H01L29/06 ,  H01L27/088 ,  H01L21/762 ,  H01L21/82 ,  H01L21/3105 ,  H01L21/02 ,  H01L29/165 ,  H01L29/16 ,  H01L29/51 ,  H01L21/8238 ,  H01L21/8234

Abstract: A semiconductor structure, such as a microchip that includes a finFET, includes fins that have a 2D material, such as Graphene, upon at least the fin sidewalls. The thickness of the 2D material sidewall may be tuned to achieve desired finFET band gap control. Neighboring fins of the semiconductor structure form fin wells. The semiconductor structure may include a fin cap upon each fin and the 2D material is formed upon the sidewalls of the fin and the bottom surface of the fin wells. The semiconductor structure may include a well-plug at the bottom of the fin wells and the 2D material is formed upon the sidewalls and upper surface of the fins. The semiconductor structure may include both fin caps and well-plugs such that the 2D material is formed only upon the sidewalls of the fins.

公开(公告)号：US09947660B1

公开(公告)日：2018-04-17

申请号：US15489920

申请日：2017-04-18

Applicant: International Business Machines Corporation

Inventor： Sami Rosenblatt ,  Rasit O. Topaloglu

IPC: H01L29/06 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/16 ,  H01L29/51 ,  H01L21/02 ,  H01L29/165 ,  H01L21/3105 ,  H01L21/82 ,  H01L21/762

CPC classification number: H01L27/0886 ,  H01L21/02378 ,  H01L21/02527 ,  H01L21/31055 ,  H01L21/76224 ,  H01L21/8213 ,  H01L21/823431 ,  H01L21/823871 ,  H01L29/0649 ,  H01L29/1606 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/517

Abstract: A semiconductor structure, such as a microchip that includes a finFET, includes fins that have a 2D material, such as Graphene, upon at least the fin sidewalls. The thickness of the 2D material sidewall may be tuned to achieve desired finFET band gap control. Neighboring fins of the semiconductor structure form fin wells. The semiconductor structure may include a fin cap upon each fin and the 2D material is formed upon the sidewalls of the fin and the bottom surface of the fin wells. The semiconductor structure may include a well-plug at the bottom of the fin wells and the 2D material is formed upon the sidewalls and upper surface of the fins. The semiconductor structure may include both fin caps and well-plugs such that the 2D material is formed only upon the sidewalls of the fins.

公开(公告)号：US09569578B1

公开(公告)日：2017-02-14

申请号：US14967877

申请日：2015-12-14

Applicant: International Business Machines Corporation

Inventor： Kafai Lai ,  Rasit O. Topaloglu

IPC: G06F17/50 ,  H01L21/027 ,  H01L21/3105 ,  H01L21/311

CPC classification number: G06F17/5068 ,  G03F7/0002 ,  H01L21/0271

Abstract: A computer implemented method of mask decomposition and optimization for directed self assembly (DSA) which includes: inputting design information of an integrated circuit that is to be patterned using a DSA process; mapping the design information into a tree graph comprising nodes and edges; searching the tree graph to identify a longest path through the tree graph; identifying a branch comprising an edge on the tree graph not on the longest path and stemming from one of the nodes on the longest path; outputting the one node on the longest path that connects to the branch as a hot spot; and modifying a photomask by removing the branch from the photomask; wherein the method is performed by one or more computing devices.

Abstract translation: 一种用于定向自组装（DSA）的面罩分解和优化的计算机实现方法，其包括：使用DSA过程输入要被图案化的集成电路的设计信息; 将设计信息映射到包括节点和边缘的树形图; 搜索树形图以识别通过树形图的最长路径; 识别包括树图上不在最长路径上的边缘并且来自最长路径上的节点之一的分支; 将连接到分支的最长路径上的一个节点作为热点输出; 以及通过从所述光掩模中移除所述分支来修改光掩模; 其中所述方法由一个或多个计算设备执行。

公开(公告)号：US20160180003A1

公开(公告)日：2016-06-23

申请号：US14573535

申请日：2014-12-17

Applicant: International Business Machines Corporation

Inventor： Stephen E. Greco ,  Rasit O. Topaloglu

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F7/70066 ,  G03F7/705 ,  G03F7/70558 ,  G06F2217/12 ,  Y02P90/265

Abstract: In an approach to determine one or more exposure areas in a reticle field and associated lithography process parameters for the one or more exposure areas, the computer receives a semiconductor design and sends the semiconductor design to a design analysis program. Additionally, the computer receives data from the design analysis program. Furthermore, the computer determines one or more exposure areas in the reticle field, and at least one lithography process parameter for each of the one or more exposure areas in the reticle field based, at least in part, on the data from the design analysis program, the semiconductor design, and one or more clustering algorithms associated with the design analysis program.

Abstract translation: 在确定掩模版领域中的一个或多个曝光区域和用于一个或多个曝光区域的相关光刻工艺参数的方法中，计算机接收半导体设计并将半导体设计发送到设计分析程序。 此外，计算机从设计分析程序接收数据。 此外，计算机至少部分地基于来自设计分析程序的数据来确定标线场中的一个或多个曝光区域，以及至少一个光刻处理参数，用于标线区域中的一个或多个曝光区域中的每一个的光刻处理参数 ，半导体设计，以及与设计分析程序相关联的一个或多个聚类算法。

公开(公告)号：US20150339422A1

公开(公告)日：2015-11-26

申请号：US14285719

申请日：2014-05-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Stephen E. Greco ,  Vincent J. McGahay ,  Rasit O. Topaloglu

IPC: G06F17/50 ,  H01L21/311 ,  H01L21/033 ,  H01L21/768

CPC classification number: G06F17/5068 ,  G06F17/50 ,  H01L21/033 ,  H01L21/0332 ,  H01L21/311 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Via-level design shapes are mapped into stitch regions of line-level design shapes design in an overlying conductive line level. A via-catching design shape is provided in an underlying conductive line level for each stitch region that does not correspond to a via-level design shape. The shapes of the stitch regions and the via-catch design shapes can be adjusted to comply with design rule constraints. Further, stitches can be optionally moved into a neighboring line-level design shape to resolve design rule conflicts. The modified design layout can eliminate via-level design shapes once all via-level design shapes are replaced with a corresponding stitch region, thereby eliminating the need to provide a via level lithographic mask. A metal interconnect structure embodying the modified design layout can be formed by employing a set of hard mask layers and without employing a lithographic mask for a via level.

Abstract translation: 通过级别的设计形状被映射到上层导线级别的线级设计形状设计的针脚区域。 对于不对应于通孔级设计形状的每个针脚区域，在底层导电线路层中提供通孔捕捉设计形状。 可以调整针迹区域和通孔捕捉设计形状的形状以符合设计规则约束。 此外，针迹可以可选地移动到相邻的线级设计形状中以解决设计规则冲突。 一旦所有通孔级设计形状被相应的针脚区域替换，修改后的设计布局可以消除通孔级设计形状，从而不需要提供通孔级光刻掩模。 体现修改后的设计布局的金属互连结构可以通过采用一组硬掩模层而不使用用于通孔级的光刻掩模来形成。

公开(公告)号：US20140284813A1

公开(公告)日：2014-09-25

申请号：US13849796

申请日：2013-03-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Stephen E. Greco ,  Rasit O. Topaloglu

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76816 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A design layout is provided such that an underlying conductive line structure underlies a stitch region in an overlying conductive line structure. A stitch-induced via structure can be formed between the underlying conductive line structure and the overlying conductive line structure when a stitch region in a hard mask layer is etched multiple times. At least one of the underlying conductive line structure and the overlying conductive line structure is electrically isolated from other conductive line structures in a same design level so as to avoid unintentional electrical shorts.

Abstract translation: 提供了一种设计布局，使得下面的导线结构位于上覆导电线结构中的针脚区域的下面。 当硬掩模层中的针脚区域被多次蚀刻时，可以在下面的导电线结构和上覆导电线结构之间形成针迹引导的通孔结构。 底层导线结构和上覆导线结构中的至少一个在相同设计级别上与其它导线结构电隔离，以避免无意的电短路。