公开(公告)号：US20190109191A1

公开(公告)日：2019-04-11

申请号：US15730306

申请日：2017-10-11

Applicant: International Business Machines Corporation

Inventor： Xin Miao ,  Kangguo Cheng ,  Chen Zhang ,  Wenyu Xu

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/10 ,  H01L29/423 ,  H01L21/02

CPC classification number: H01L29/0673 ,  H01L21/02381 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02507 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02587 ,  H01L29/1033 ,  H01L29/4232 ,  H01L29/66522 ,  H01L29/775

Abstract: A method for fabricating a semiconductor structure includes forming a nanosheet stack on a base. The nanosheet stack comprises one or more first nanosheet layers each comprised of a first material and one or more second nanosheet layers each comprised of a second material different from the first material. The nanosheet stack is recessed. Inner spacers comprising a third material are formed. Forming the inner spacers includes converting the first material corresponding to outer portions of each of the one or more first nanosheet layers into the third material.

公开(公告)号：US20190051535A1

公开(公告)日：2019-02-14

申请号：US16160366

申请日：2018-10-15

Applicant: International Business Machines Corporation

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Juntao Li ,  Xin Miao

IPC: H01L21/3105 ,  H01L29/66 ,  H01L29/78 ,  H01L29/775 ,  H01L21/02 ,  H01L29/423 ,  H01L29/417 ,  H01L29/06 ,  H01L21/324 ,  H01L21/306

CPC classification number: H01L21/3105 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/30608 ,  H01L21/324 ,  H01L29/0676 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696 ,  H01L2029/7858

Abstract: Techniques for producing stacked SiGe nanowires using a condensation process without parasitic Ge nanowires as an undesired by-product. In one aspect, a method of forming SiGe nanowires includes the steps of: forming a stack of alternating Si and SiGe layers on a wafer; patterning fins in the stack; selectively thinning the SiGe layers in the fins such that the Si and SiGe layers give the fins an hourglass shape; burying the fins in an oxide material; and annealing the fins under conditions sufficient to diffuse Ge from the SiGe layers in the fins to the Si layers in the fins to form the SiGe nanowires. A FET device and method for formation thereof are also provided.

公开(公告)号：US10153367B2

公开(公告)日：2018-12-11

申请号：US15206939

申请日：2016-07-11

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Xin Miao ,  Wenyu Xu ,  Chen Zhang

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/02 ,  H01L29/08 ,  H01L21/033 ,  H01L21/8234 ,  H01L29/10

Abstract: A semiconductor structure and a method a method of forming a vertical FET (Field-Effect Transistor), includes growing a bottom source-drain layer of a second type on a substrate of a first type, growing a channel layer on the bottom source-drain layer, forming a first fin from the channel layer with mask on top of the first fin. A width of the mask is wider than a final first fin width.

公开(公告)号：US20180351002A1

公开(公告)日：2018-12-06

申请号：US16057579

申请日：2018-08-07

Applicant: International Business Machines Corporation ,  Globalfoundries Inc.

Inventor： Kangguo Cheng ,  Xin Miao ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/78696 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78687

Abstract: In one aspect, a method of forming a semiconductor device includes the steps of: forming an alternating series of sacrificial/active layers on a wafer and patterning it into at least one nano device stack; forming a dummy gate on the nano device stack; patterning at least one upper active layer in the nano device stack to remove all but a portion of the at least one upper active layer beneath the dummy gate; forming spacers on opposite sides of the dummy gate covering the at least one upper active layer that has been patterned; forming source and drain regions on opposite sides of the nano device stack, wherein the at least one upper active layer is separated from the source and drain regions by the spacers; and replacing the dummy gate with a replacement gate. A masking process is also provided to tailor the effective device width of select devices.

公开(公告)号：US20180350909A1

公开(公告)日：2018-12-06

申请号：US16042498

申请日：2018-07-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Josephine B. Chang ,  Bruce B. Doris ,  Michael A. Guillorn ,  Isaac Lauer ,  Xin Miao

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L29/775 ,  H01L29/417

CPC classification number: H01L29/0673 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

Abstract: Field effect transistors include a stack of nanowires of vertically arranged channel layers. A source and drain region is disposed at respective ends of the vertically arranged channel layers. A gate stack is formed over, around, and between the vertically arranged channel layers. Internal spacers are each formed between the gate stack and a respective source or drain region, with at least one pair of spacers being positioned above an uppermost channel layer.

公开(公告)号：US20180350695A1

公开(公告)日：2018-12-06

申请号：US15608159

申请日：2017-05-30

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Xin Miao ,  Wenyu Xu ,  Chen Zhang

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L21/823487 ,  H01L21/823437 ,  H01L29/1037 ,  H01L29/7827

Abstract: A method for manufacturing a semiconductor device includes forming a plurality of fins on a substrate, wherein a hardmask is formed on each of the plurality of fins, forming a gate structure around the plurality of fins, selectively depositing a dummy dielectric on the hardmask on each of the plurality of fins, depositing a dielectric layer on the gate structure and around the dummy dielectrics, selectively removing the dummy dielectrics and the hardmasks with respect to the dielectric layer and the gate structure to create a plurality of openings exposing portions of the gate structure, and selectively removing the exposed portions of the gate structure through the plurality of the openings.

公开(公告)号：US10141441B2

公开(公告)日：2018-11-27

申请号：US15811830

申请日：2017-11-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Xin Miao ,  Peng Xu ,  Chen Zhang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10

Abstract: A method of making a vertical transistor device includes forming a front gate and a back gate opposite a major surface of a substrate. The front gate and the back gate are symmetric and arranged on opposing sides of a channel between the front gate and the back gate. The channel extends from a drain to a source. The method includes disposing a mask to cover the front gate and removing the back gate. The method further includes replacing the back gate with a layer of insulator and another back gate stack. The another back gate stack only covers a junction between the channel and the source, and remaining portions of the back gate are the layer of insulator.

公开(公告)号：US20180301451A1

公开(公告)日：2018-10-18

申请号：US16005124

申请日：2018-06-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Xin Miao ,  Philip J. Oldiges ,  Wenyu Xu ,  Chen Zhang

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6656 ,  H01L29/66666 ,  H01L29/7827

Abstract: A method for reducing parasitic capacitance of a semiconductor structure is provided. The method includes forming a fin structure over a substrate, forming a first source/drain region between the fin structure and the substrate, forming first spacers adjacent the fin structure, forming second spacers adjacent the first source/drain region and recessing the first source/drain region in exposed areas. The method further includes forming a shallow trench isolation (STI) region within the exposed areas of the recessed first source/drain region, depositing a bottom spacer over the STI region, forming a metal gate stack over the bottom spacer, depositing a top spacer over the metal gate stack, cutting the metal gate stack, forming a second source/drain region over the fin structure, and forming contacts such the STI region extends a length between the metal gate stack and the first source/drain region.

公开(公告)号：US10103246B2

公开(公告)日：2018-10-16

申请号：US15177362

申请日：2016-06-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Xin Miao ,  Wenyu Xu ,  Chen Zhang

IPC: H01L29/66 ,  H01L21/225 ,  H01L21/02 ,  H01L21/308 ,  H01L29/423 ,  H01L29/40 ,  H01L21/3065 ,  H01L29/78

Abstract: A method of forming a vertical fin field effect transistor with a self-aligned gate structure, comprising forming a plurality of vertical fins on a substrate, forming gate dielectric layers on opposite sidewalls of each vertical fin, forming a gate fill layer between the vertical fins, forming a fin-cut mask layer on the gate fill layer, forming one or more fin-cut mask trench(es) in the fin-cut mask layer, and removing portions of the gate fill layer and vertical fins not covered by the fin-cut mask layer to form one or more fin trench(es), and two or more vertical fin segments from each of the plurality of vertical fins, having a separation distance, D1, between two vertical fin segments.

公开(公告)号：US20180277675A1

公开(公告)日：2018-09-27

申请号：US15966232

申请日：2018-04-30

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Xin Miao ,  Philip J. Oldiges ,  Wenyu Xu ,  Chen Zhang

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/08

CPC classification number: H01L29/7827 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/66666

Abstract: Provided is a method for forming a semiconductor structure. In embodiments of the invention, the method includes forming a semiconductor fin on a source/drain region, forming a liner including a first dielectric material along sidewalls of the semiconductor fin and along sidewalls of the source/drain region, forming a second dielectric material along sidewalls of the liner including the first dielectric material, and removing the liner including the first dielectric material from sidewalls of the semiconductor fin. Removing the liner including the first dielectric material includes exposing portions of the source/drain region. The method further includes forming a spacer layer on the second dielectric material and portions of the source/drain region exposed by removing the liner including the first dielectric material and forming a gate material on the spacer layer.