公开(公告)号：US09608068B2

公开(公告)日：2017-03-28

申请号：US14819244

申请日：2015-08-05

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Pouya Hashemi ,  Hong He ,  Alexander Reznicek

IPC: H01L29/10 ,  H01L21/762 ,  H01L21/02

CPC classification number: H01L29/1054 ,  H01L21/76254 ,  H01L29/7842

Abstract: A method is provided for forming an integrated circuit. A trench is formed in a substrate. Subsequently, a silicon-germanium feature is formed in the trench, and an etch stop layer is formed on the substrate and on the silicon-germanium feature. Lastly, a silicon device layer is formed on the etch stop layer. The silicon device layer has a tensily-strained region overlying the silicon-germanium feature. Regions of the silicon device layer not overlying the silicon-germanium feature are less strained than the tensily-strained region. The tensily-strained region of the silicon device layer may be further processed into channel features in n-type field effect transistors with improved charge carrier mobilities and device drive currents.

公开(公告)号：US20170076992A1

公开(公告)日：2017-03-16

申请号：US14851838

申请日：2015-09-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hong He ,  Juntao Li ,  Junli Wang ,  Chih-Chao Yang

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/306

CPC classification number: H01L21/823821 ,  H01L21/823878 ,  H01L27/1211

Abstract: A method for forming a semiconductor device includes etching first fins into a bulk semiconductor substrate and exposing a portion of the first fins through a first dielectric layer formed over the first fins. A first film is deposited over the first fins in a region for n-type devices, and a second film is deposited over the first fins in a region for p-type devices. The first film and the second film are etched to form second fins in the regions for n-type devices and for the region for p-type devices. The second fins are protected. The first fins are removed from the first dielectric layer to form an isolation layer separating the second fins from the substrate.

Abstract translation: 一种用于形成半导体器件的方法包括将第一鳍片蚀刻成体半导体衬底，并使第一鳍片的一部分通过形成在第一鳍片上的第一介电层暴露。 第一膜沉积在用于n型器件的区域中的第一鳍片上，并且第二膜沉积在用于p型器件的区域中的第一鳍片上。 蚀刻第一膜和第二膜以在n型器件的区域和用于p型器件的区域中形成第二鳍。 第二个翅片被保护。 从第一电介质层移除第一散热片以形成将第二散热片与衬底隔开的隔离层。

公开(公告)号：US20170053838A1

公开(公告)日：2017-02-23

申请号：US14833350

申请日：2015-08-24

Applicant: International Business Machines Corporation

Inventor： Bruce B. Doris ,  Hong He ,  Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Fee Li Lie ,  Stuart A. Sieg

IPC: H01L21/84 ,  H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L21/762 ,  H01L21/306

CPC classification number: H01L21/845 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/76213 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A method for forming a fin on a substrate comprises patterning and etching a layer of a first semiconductor material to define a strained fin, depositing a layer of a second semiconductor material over the fin, the second semiconductor material operative to maintain the a strain in the strained fin, etching to remove a portion of the second semiconductor material to define a cavity that exposes a portion of the fin, etching to remove the exposed portion of the fin such that the fin is divided into a first segment and a second segment, and depositing an insulator material in the cavity, the insulator material contacting the first segment of the fin and the second segment of the fin.

公开(公告)号：US09576979B2

公开(公告)日：2017-02-21

申请号：US14722237

申请日：2015-05-27

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Hong He ,  Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Juntao Li ,  Fee Li Lie ,  Derrick Liu ,  Chun Wing Yeung

IPC: H01L21/308 ,  H01L27/12 ,  H01L29/66 ,  H01L29/161 ,  H01L21/84 ,  H01L29/78

CPC classification number: H01L27/1211 ,  H01L21/845 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7849

Abstract: A semiconductor structure includes a first strained fin portion and a second strained fin portion, a pair of inactive inner gate structures upon respective strained fin portions, and spacers upon outer sidewalls surfaces of the inactive inner gate structures, upon the inner sidewall surfaces of the inactive inner gate structures, and upon the first strained fin portion and the second strained fin portion end surfaces. The first strained fin portion and the second strained fin portion end surfaces are coplanar with respective inner sidewall surfaces of the inactive inner gate structures. The spacer formed upon the end surfaces limits relaxation of the first strained fin portion and the second strained fin portion and limits shorting between the first strained fin portion and the second strained fin portion.

Abstract translation: 半导体结构包括第一应变翅片部分和第二应变翅片部分，在相应的应变翅片部分上的一对无效内部门结构，以及在非活性内部门结构的外侧壁表面上的间隔物， 内门结构，以及在第一应变翅片部分和第二应变翅片部分端表面上。 第一应变翅片部分和第二应变翅片部分端面与非活性内部门结构的相应的内侧壁表面共面。 形成在端面上的间隔限制了第一应变翅片部分和第二应变翅片部分的松弛，并且限制了第一应变翅片部分和第二应变翅片部分之间的短路。

公开(公告)号：US09570299B1

公开(公告)日：2017-02-14

申请号：US14847619

申请日：2015-09-08

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Hong He ,  Ali Khakifirooz ,  Juntao Li

IPC: H01L21/02 ,  H01L21/306 ,  H01L21/324 ,  H01L29/06 ,  H01L29/161 ,  G01N33/00 ,  B82Y15/00 ,  B82Y40/00

CPC classification number: H01L21/02694 ,  B82Y15/00 ,  B82Y30/00 ,  B82Y40/00 ,  G01N33/0036 ,  G01N33/005 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02606 ,  H01L21/02647 ,  H01L21/02664 ,  H01L21/18 ,  H01L21/30604 ,  H01L21/324 ,  H01L29/0649 ,  H01L29/0669 ,  H01L29/0676 ,  H01L29/161 ,  H01L29/165 ,  Y10S977/814 ,  Y10S977/89 ,  Y10S977/90 ,  Y10S977/957

Abstract: Techniques for forming nanostructured materials are provided. In one aspect of the invention, a method for forming nanotubes on a buried insulator includes the steps of: forming one or more fins in a SOI layer of an SOI wafer, wherein the SOI wafer has a substrate separated from the SOI layer by the buried insulator; forming a SiGe layer on the fins; annealing the SiGe layer under conditions sufficient to drive-in Ge from the SiGe layer into the fins and form a SiGe shell completely surrounding each of the fins; and removing the fins selective to the SiGe shell, wherein the SiGe shell which remains forms the nanotubes on the buried insulator. A nanotube structure and method of forming a nanotube device are also provided.

Abstract translation: 提供了形成纳米结构材料的技术。 在本发明的一个方面，一种用于在埋层绝缘体上形成纳米管的方法包括以下步骤：在SOI晶片的SOI层中形成一个或多个翅片，其中SOI晶片具有通过埋置的SOI层与SOI层分离的衬底 绝缘子; 在翅片上形成SiGe层; 在足以从SiGe层驱入Ge到翅片中的条件下退火SiGe层，并形成完全围绕每个翅片的SiGe壳; 并且去除对SiGe壳体有选择性的散热片，其中剩余的SiGe壳体在埋入的绝缘体上形成纳米管。 还提供了纳米管结构和形成纳米管器件的方法。

公开(公告)号：US09515141B1

公开(公告)日：2016-12-06

申请号：US15135844

申请日：2016-04-22

Applicant: International Business Machines Corporation

Inventor： Bruce B. Doris ,  Hong He ,  Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Fee Li Lie

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/08 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66 ,  H01L21/265 ,  H01L21/324

CPC classification number: H01L29/66795 ,  H01L21/2253 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/324 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851

Abstract: A method for fabricating a semiconductor device, the method comprises forming a fin on a substrate, forming a dummy gate stack on the fin and the substrate, removing a portion of an exposed portion of the fin, forming a source/drain region on an exposed portion of the fin, forming a conductive contact on the source/drain region, removing the dummy gate stack to expose a channel region of the fin, implanting ions in the channel region of the fin, performing an annealing process, and forming a gate stack on the channel region of the fin.

公开(公告)号：US20160351448A1

公开(公告)日：2016-12-01

申请号：US15086440

申请日：2016-03-31

Applicant: International Business Machines Corporation

Inventor： Hsueh-Chung H. Chen ,  Hong He ,  Juntao Li ,  Chih-Chao Yang ,  Yunpeng Yin

IPC: H01L21/768

CPC classification number: F24S30/452 ,  E04B1/34357 ,  E04B1/346 ,  E04B7/163 ,  F24S20/61 ,  F24S2030/18 ,  H01L21/31144 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53238 ,  Y02A30/22 ,  Y02B10/20 ,  Y02E10/47

Abstract: A method for fabricating a self-aligned via structure includes forming a tri-layer mask on an ILD layer over a lower metal wiring layer, the tri-layer mask includes first and second insulating layers and a metal layer in between the insulating layers; defining a trench pattern through the first insulating layer and metal layer, the trench pattern having a first width; defining a first via pattern in a lithographic mask over the trench pattern, the first via pattern having a second width that is larger than the first width; growing a metal capping layer on an exposed sidewall of the trench pattern to decrease the first width to a third width that defines a second via pattern; transferring the trench pattern into the ILD layer to form a trench; and transferring the second via pattern through the ILD layer and into the metal wiring layer to form a via.

公开(公告)号：US09508713B2

公开(公告)日：2016-11-29

申请号：US14198005

申请日：2014-03-05

Applicant: International Business Machines Corporation

Inventor： Hong He ,  Chiahsun Tseng ,  Chun-Chen Yeh ,  Yunpeng Yin

IPC: H01L27/088 ,  H01L21/308 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/12 ,  H01L29/16 ,  H01L29/78 ,  H01L21/84

CPC classification number: H01L27/0886 ,  H01L21/3085 ,  H01L21/3088 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/16 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a fin-based field-effect transistor device includes forming one or more first fins comprising silicon on a substrate, forming epitaxial layers on sides of the one or more first fins, and removing the one or more first fins to form a plurality of second fins.

Abstract translation: 一种形成鳍状场效应晶体管器件的方法包括在衬底上形成包括硅的一个或多个第一鳍片，在一个或多个第一鳍片的侧面上形成外延层，以及去除一个或多个第一鳍片以形成 多个第二鳍片。

公开(公告)号：US20160322501A1

公开(公告)日：2016-11-03

申请号：US14699491

申请日：2015-04-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Hong He ,  Juntao Li

IPC: H01L29/78 ,  H01L21/322 ,  H01L21/02 ,  H01L21/324 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/66795 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/18 ,  H01L21/322 ,  H01L21/3221 ,  H01L21/324 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7851 ,  H01L29/7853

Abstract: A silicon germanium alloy is formed on sidewall surfaces of a silicon fin. An oxidation process or a thermal anneal is employed to convert a portion of the silicon fin into a silicon germanium alloy fin. In some embodiments, the silicon germanium alloy fin has a wide upper portion and a narrower lower portion. In such an embodiment, the wide upper portion has a greater germanium content than the narrower lower portion. In other embodiments, the silicon germanium alloy fin has a narrow upper portion and a wider lower portion. In this embodiment, the narrow upper portion of the silicon germanium alloy fin has a greater germanium content than the wider lower portion of the silicon germanium alloy fin.

Abstract translation: 在硅片的侧壁表面上形成硅锗合金。 采用氧化工艺或热退火将硅片的一部分转换成硅锗合金翅片。 在一些实施例中，硅锗合金翅片具有宽的上部和较窄的下部。 在这样的实施例中，宽的上部具有比较窄的下部更大的锗含量。 在其他实施例中，硅锗合金翅片具有窄的上部和较宽的下部。 在本实施例中，硅锗合金翅片的较窄上部具有比硅锗合金翅片的较宽下部更大的锗含量。

公开(公告)号：US20160247883A1

公开(公告)日：2016-08-25

申请号：US15078024

申请日：2016-03-23

Applicant: International Business Machines Corporation

Inventor： Hong He ,  Juntao Li ,  Junli Wang ,  Chih-Chao Yang

IPC: H01L29/161 ,  H01L29/78

CPC classification number: H01L21/02636 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/0259 ,  H01L21/02639 ,  H01L27/1211 ,  H01L29/161 ,  H01L29/785

Abstract: A method of forming semiconductor fins includes forming a plurality of sacrificial template fins from a first semiconductor material; epitaxially growing fins of a second semiconductor material on exposed sidewall surfaces of the sacrificial template fins; and removing the plurality of sacrificial template fins.

Abstract translation: 形成半导体翅片的方法包括从第一半导体材料形成多个牺牲模板翅片; 在牺牲模板翅片的暴露的侧壁表面上外延生长第二半导体材料的翅片; 以及去除所述多个牺牲模板翅片。