公开(公告)号：US06656798B2

公开(公告)日：2003-12-02

申请号：US09965919

申请日：2001-09-28

申请人： Helmut Tews ,  Oleg Gluschenkov ,  Mary Weybright

发明人： Helmut Tews ,  Oleg Gluschenkov ,  Mary Weybright

IPC分类号： H01L21336

CPC分类号： H01L29/517 ,  H01L21/28238 ,  H01L21/76224 ,  H01L21/823481 ,  H01L29/42368

摘要： Disclosed is a method of processing a semiconductor gate structure on a semiconductor wafer, the method comprising providing a semiconductor structure with an active device area capped with a pad oxide layer bounded by one or more isolation trenches, providing a sacrificial oxide layer by thickening said pad oxide layer to a desired oxide thickness, in using said thickened pad oxide layer as said sacrificial oxide layer for device implantation, stripping said sacrificial pad oxide layer after use, and capping said semiconductor gate with a final gate oxide layer.

摘要翻译： 公开了一种在半导体晶片上处理半导体栅极结构的方法，该方法包括提供半导体结构，该半导体结构具有覆盖有由一个或多个隔离沟槽限定的焊盘氧化物层的有源器件区域，通过增厚所述焊盘来提供牺牲氧化物层 使用所述增厚衬垫氧化物层作为用于器件注入的牺牲氧化物层，在使用之后剥离所述牺牲衬垫氧化物层，并用最终栅极氧化物层封装所述半导体栅极。

公开(公告)号：US06451662B1

公开(公告)日：2002-09-17

申请号：US09970635

申请日：2001-10-04

申请人： Michael Chudzik ,  Oleg Gluschenkov ,  Raj Jammy ,  Uwe Schroeder ,  Helmut Tews

发明人： Michael Chudzik ,  Oleg Gluschenkov ,  Raj Jammy ,  Uwe Schroeder ,  Helmut Tews

IPC分类号： H01L2120

CPC分类号： H01L27/10861 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02247 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/02326 ,  H01L21/02332 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/31662 ,  H01L21/32105

摘要： An improved capacitor is formed by a process where an improved node dielectric layer is formed with an improved dielectric constant by performing an Free Radical Enhanced Rapid Thermal Oxidation (FRE RTO) step during formation of the node dielectric layer. Use of an FRE RTO step instead of the conventional furnace oxidation step produces a cleaner oxide with a higher dielectric constant and higher capacitance. Other specific embodiments of the invention include improved node dielectric layer by one or more additional nitridation steps, done by either Remote Plasma Nitridation (RPN), Rapid Thermal Nitridation (RTN), Decoupled Plasma Nitridation (DPN) or other nitridation method; selective oxidation; use of a metal layer rather than a SiN layer as the dielectric base; and selective oxidation of the metal layer.

摘要翻译： 通过在形成节点介质层期间通过执行自由基增强快速热氧化（FRE RTO）步骤而改进的介电常数形成改进的节点电介质层的工艺形成改进的电容器。 使用FRE RTO步骤代替常规炉氧化步骤产生具有更高介电常数和较高电容的清洁氧化物。 本发明的其它具体实施方案包括通过远程等离子体氮化（RPN），快速热氮化（RTN），去耦等离子体氮化（DPN）或其它氮化方法进行的一个或多个另外的氮化步骤改进的节点电介质层; 选择性氧化; 使用金属层而不是SiN层作为电介质基底; 和金属层的选择性氧化。

公开(公告)号：US5980631A

公开(公告)日：1999-11-09

申请号：US992182

申请日：1997-12-17

申请人： Helmut Tews ,  Meinrad Schienle ,  Robert Averbeck

发明人： Helmut Tews ,  Meinrad Schienle ,  Robert Averbeck

IPC分类号： C30B29/38 ,  H01L21/20 ,  H01L21/203 ,  H01L33/00 ,  H01S5/323 ,  C30B23/00

CPC分类号： H01L33/0075 ,  H01L21/02458 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02631 ,  H01L33/007 ,  H01S5/32341

摘要： A method for manufacturing III-V semiconductor layers containing nitrogen whereby during the growth of the layers, the setting of the material sources for Al, In and Ga remains fixed. During the transition to the growth of a layer with another mixed-crystal composition, the nitrogen flow is altered. A greater nitrogen flow leads to an increased installation of the more weakly bound group III elements into the growing material.

摘要翻译： 一种用于制造含有氮的III-V半导体层的方法，由此在层的生长期间，Al，In和Ga的材料源的固定保持固定。 在转变为具有另一种混合晶体组合物的层的生长过程中，氮气流被改变。 较大的氮气流导致将更弱的III族元素安装到生长材料中。

公开(公告)号：US5070028A

公开(公告)日：1991-12-03

申请号：US678047

申请日：1991-04-01

申请人： Helmut Tews ,  Hans-Peter Zwicknagl

发明人： Helmut Tews ,  Hans-Peter Zwicknagl

IPC分类号： H01L29/205 ,  H01L21/331 ,  H01L29/06 ,  H01L29/73 ,  H01L29/737

CPC分类号： H01L29/66318 ,  H01L29/0649 ,  Y10S148/01

摘要： A method for manufacturing a heterobipolar transistor having and at least greatly diminished extrinsic base-collector capacitance provides an insulation implantation in a sub-collector layer grown onto a semi-insulating substrate via a first mask that covers a region provided for the sub-collector to be constructed or the sub-collector is formed by doping the semi-insulating substrate through a mask. The semiconductor layers for the collector, the base and the emitter, the sub-collector being fashioned in a limited region provided therefore and the emitter is aligned on the sub-collector with a second mask.

摘要翻译： 用于制造具有并且至少大大减小的非本征基极 - 集电极电容器的异质双极晶体管的方法通过覆盖设置用于次集电极的区域的第一掩模在半绝缘基板上生长的子集电极层中提供绝缘注入 或通过掩模掺杂半绝缘基板形成子集电极。 用于集电极，基极和发射极的半导体层，子集电极的形状设计在有限的区域内，并且发射极与第二掩模在子集电极上对准。

公开(公告)号：US4904612A

公开(公告)日：1990-02-27

申请号：US374617

申请日：1989-06-30

申请人： Hans-Peter Zwicknagl ,  Josef Willer ,  Helmut Tews

发明人： Hans-Peter Zwicknagl ,  Josef Willer ,  Helmut Tews

IPC分类号： H01L29/73 ,  H01L21/28 ,  H01L21/331 ,  H01L29/737

CPC分类号： H01L29/66272 ,  H01L21/28 ,  H01L29/66318 ,  H01L29/7371 ,  Y10S148/011 ,  Y10S438/951

摘要： A method for the manufacture of a planar, self-aligned emitter-base complex, whereby a semiconductor layer structure standard for hetero-bipolar transistors is first grown on a substrate, the base regions are subsequently etching through a mask technique and are provided with the base metallization and with a first dielectric layer and insulation implantations and spacers for electrical insulation of the base are manufactured, and, following thereupon, the emitter region is provided with the emitter metallization and with a third dielectric layer.

摘要翻译： 一种用于制造平面，自对准的发射极 - 基极复合体的方法，由此首先在衬底上生长用于异质双极晶体管的半导体层结构标准，然后通过掩模技术蚀刻基底区域，并且提供 基底金属化和第一介电层，并且制造用于基底的电绝缘的绝缘注入和间隔物，随后，发射极区域设置有发射极金属化和第三介电层。

公开(公告)号：US09240462B2

公开(公告)日：2016-01-19

申请号：US12888938

申请日：2010-09-23

申请人： Juergen Holz ,  Klaus Schruefer ,  Helmut Tews

发明人： Juergen Holz ,  Klaus Schruefer ,  Helmut Tews

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L29/417

CPC分类号： H01L29/66636 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/3205 ,  H01L29/0653 ,  H01L29/41783

摘要： A method for fabricating a field-effect transistor with local source/drain insulation. The method includes forming and patterning a gate stack with a gate layer and a gate dielectric on a semiconductor substrate; forming source and drain depressions at the gate stack in the semiconductor substrate; forming a depression insulation layer at least in a bottom region of the source and drain depressions; and filling the at least partially insulated source and drain depressions with a filling layer for realizing source and drain regions.

摘要翻译： 一种制造具有局部源极/漏极绝缘的场效应晶体管的方法。 该方法包括在半导体衬底上形成和图案化具有栅极层和栅极电介质的栅叠层; 在半导体衬底中的栅极堆叠处形成源极和漏极凹陷; 至少在所述源极和漏极凹陷的底部区域中形成凹陷绝缘层; 以及用用于实现源极和漏极区域的填充层填充所述至少部分绝缘的源极和漏极凹部。

公开(公告)号：US20100264472A1

公开(公告)日：2010-10-21

申请号：US12830048

申请日：2010-07-02

申请人： Rodger Fehlhaber ,  Helmut Tews

发明人： Rodger Fehlhaber ,  Helmut Tews

IPC分类号： H01L29/78

CPC分类号： H01L29/7851 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L29/42384 ,  H01L29/66772 ,  H01L29/66795

摘要： A patterning method with a filling material with a T-shaped cross section is used as a mask during patterning to produce structures having sublithographic dimensions, such as a double-fin field effect transistor.

摘要翻译： 在图案化期间，使用具有T形横截面的填充材料的图案化方法来制造具有亚光刻尺寸的结构，例如双翅片场效应晶体管。

公开(公告)号：US07786530B2

公开(公告)日：2010-08-31

申请号：US10521528

申请日：2003-06-12

申请人： Ronald Kakoschke ,  Helmut Tews

发明人： Ronald Kakoschke ,  Helmut Tews

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L21/823412 ,  H01L21/823418 ,  H01L21/823425 ,  H01L29/66666 ,  H01L29/7827

摘要： A vertical field-effect transistor having a semiconductor layer, in which a doped channel region is arranged along a depression. A “buried” terminal region leads as far as a surface of the semiconductor layer. The field-effect transistor also has a doped terminal region near an opening of the depression as well as the doped terminal region remote from the opening, a control region arranged in the depression, and an electrical insulating region between the control region and the channel region. The terminal region remote from the opening leads as far as a surface containing the opening or is electrically conductively connected to an electrically conductive connection leading to the surface. The control region is arranged in only one depression. The field-effect transistor is a drive transistor at a word line or at a bit line of a memory cell array.

摘要翻译： 具有半导体层的垂直场效应晶体管，其中掺杂沟道区沿着凹陷布置。 “埋入”端子区域导通至半导体层的表面。 场效应晶体管还具有靠近凹陷的开口的掺杂端子区域以及远离开口的掺杂端子区域，布置在凹陷中的控制区域以及控制区域和沟道区域之间的电绝缘区域 。 远离开口的端子区域引出至包含开口的表面，或者导电地连接到通向该表面的导电连接。 控制区域仅布置在一个凹部中。 场效应晶体管是位于存储单元阵列的字线或位线处的驱动晶体管。

公开(公告)号：US07528453B2

公开(公告)日：2009-05-05

申请号：US10530634

申请日：2003-09-19

申请人： Jürgen Holz ,  Klaus Schrüfer ,  Helmut Tews

发明人： Jürgen Holz ,  Klaus Schrüfer ,  Helmut Tews

IPC分类号： H01L27/088

CPC分类号： H01L29/66636 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/3205 ,  H01L29/0653 ,  H01L29/41783

摘要： A field-effect transistor (FET) with local source-drain insulation is described. The FET includes a semiconductor substrate, source and drain depressions, a depression insulation layer, an electrically conductive filling layer, a gate dielectric, and a gate layer. The depression insulation layer is formed at least in bottom regions of the source and drain depressions. The electrically conductive filling layer realizes source and drain regions and fills the source and drain depressions at a surface of the depression insulation layer. The gate dielectric is formed at a substrate surface between the source and drain depressions. The gate layer (is formed at a surface of the gate dielectric. The source and drain depressions have, in an upper region, a widening with a predetermined death for realizing defined channel connection regions.

摘要翻译： 描述了具有局部源极 - 漏极绝缘的场效应晶体管（FET）。 FET包括半导体衬底，源极和漏极凹陷，凹陷绝缘层，导电填充层，栅极电介质和栅极层。 凹陷绝缘层至少形成在源极和漏极凹陷的底部区域中。 导电填充层实现源极和漏极区域并填充凹陷绝缘层的表面处的源极和漏极凹陷。 栅极电介质形成在源极和漏极凹陷之间的衬底表面处。 栅极层形成在栅极电介质的表面。 源极和漏极凹陷在上部区域中具有用于实现限定的沟道连接区域的预定深度的加宽。

公开(公告)号：US20080290406A1

公开(公告)日：2008-11-27

申请号：US12143204

申请日：2008-06-20

申请人： Helmut Tews

发明人： Helmut Tews

IPC分类号： H01L29/78

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/66833 ,  H01L29/7828 ,  H01L29/78642 ,  H01L29/7883 ,  H01L29/7885 ,  H01L29/792

摘要： A method for producing a field effect transistor, in which a plurality of layers are in each case deposited, planarized and etched back, in particular a gate electrode layer, is disclosed. This method allows the manufacturing of transistors having outstanding electrical properties and having outstanding reproducibility.

摘要翻译： 公开了一种场效应晶体管的制造方法，其中在各种情况下沉积，平坦化和回蚀刻多个层，特别是栅极电极层。 该方法允许制造具有优异的电性能并具有出色的再现性的晶体管。