公开(公告)号：US20100330803A1

公开(公告)日：2010-12-30

申请号：US12876721

申请日：2010-09-07

Applicant: Meng-Jen Wang

Inventor： Meng-Jen Wang

IPC: H01L21/768

CPC classification number: H01L21/76898

Abstract: The present invention relates to a method for forming vias in a substrate, including the following steps: (a) providing a substrate having a first surface and a second surface; (b) forming a groove on the substrate; (c) filling the groove with a conductive metal; (d) removing part of the substrate which surrounds the conductive metal, wherein the conductive metal is maintained so as to form an accommodating space between the conductive metal and the substrate; (e) forming an insulating material in the accommodating space; and (f) removing part of the second surface of the substrate to expose the conductive metal and the insulating material. In this way, thicker insulating material can be formed in the accommodating space, and the thickness of the insulating material in the accommodating space is even.

Abstract translation: 本发明涉及一种在衬底中形成通孔的方法，包括以下步骤：（a）提供具有第一表面和第二表面的衬底; （b）在基板上形成凹槽; （c）用导电金属填充凹槽; （d）去除围绕所述导电金属的所述衬底的一部分，其中所述导电金属被保持以在所述导电金属和所述衬底之间形成容纳空间; （e）在容纳空间中形成绝缘材料; 和（f）去除衬底的第二表面的一部分以暴露导电金属和绝缘材料。 以这种方式，可以在容纳空间中形成更厚的绝缘材料，并且容纳空间中的绝缘材料的厚度是均匀的。

公开(公告)号：US20100327442A1

公开(公告)日：2010-12-30

申请号：US12876907

申请日：2010-09-07

Applicant: Meng-Jen Wang ,  Wei-Chung Wang

Inventor： Meng-Jen Wang ,  Wei-Chung Wang

IPC: H01L23/498

CPC classification number: H01L23/5389 ,  H01L21/481 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/2518 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2224/82 ,  H01L2924/00

Abstract: The present invention relates to a package and the method for making the same, and a stacked package. The method for making the package includes the following steps: (a) providing a carrier having a plurality of platforms; (b) providing a plurality of dice, and disposing the dice on the platforms; (c) performing a reflow process so that the dice are self-aligned on the platforms; (d) forming a molding compound in the gaps between the dice, and (e) performing a cutting process so as to form a plurality of packages. Since the dice are self-aligned on the platforms during the reflow process, a die attach machine with low accuracy can achieve highly accurate placement.

Abstract translation: 封装及其制造方法技术领域本发明涉及一种封装及其制造方法以及堆叠封装。 制造包装的方法包括以下步骤：（a）提供具有多个平台的载体; （b）提供多个骰子，并将骰子放置在平台上; （c）进行回流处理，使得骰子在平台上自对准; （d）在骰子之间的间隙中形成模塑料，和（e）进行切割处理以便形成多个包装。 由于在回流过程中骰子在平台上自对准，所以精度低的贴片机可以实现高精度的放置。

公开(公告)号：US07816265B2

公开(公告)日：2010-10-19

申请号：US12183140

申请日：2008-07-31

Applicant: Meng-Jen Wang

Inventor： Meng-Jen Wang

IPC: H01L21/44

CPC classification number: H01L21/76898

Abstract: A method for forming vias in a substrate, including the following steps: (a) providing a substrate having a first surface and a second surface; (b) forming a groove on the substrate; (c) filling the groove with a conductive metal; (d) removing part of the substrate which surrounds the conductive metal, wherein the conductive metal is maintained so as to form an accommodating space between the conductive metal and the substrate; (e) forming an insulating material in the accommodating space; and (f) removing part of the second surface of the substrate to expose the conductive metal and the insulating material. In this way, thicker insulating material can be formed in the accommodating space, and the thickness of the insulating material in the accommodating space is even.

Abstract translation: 一种在衬底中形成通孔的方法，包括以下步骤：（a）提供具有第一表面和第二表面的衬底; （b）在基板上形成凹槽; （c）用导电金属填充凹槽; （d）去除围绕所述导电金属的所述衬底的一部分，其中所述导电金属被保持以在所述导电金属和所述衬底之间形成容纳空间; （e）在容纳空间中形成绝缘材料; 和（f）去除衬底的第二表面的一部分以暴露导电金属和绝缘材料。 以这种方式，可以在容纳空间中形成更厚的绝缘材料，并且容纳空间中的绝缘材料的厚度是均匀的。

公开(公告)号：US20090321916A1

公开(公告)日：2009-12-31

申请号：US12484860

申请日：2009-06-15

Applicant: Meng-Jen Wang ,  Chien-Yu Chen

Inventor： Meng-Jen Wang ,  Chien-Yu Chen

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L21/76898 ,  H01L21/486 ,  H01L23/147 ,  H01L23/49827 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: A semiconductor structure, a method for manufacturing a semiconductor structure and a semiconductor package are provided. The method for manufacturing a semiconductor structure includes the following steps. Firstly, a silicon substrate is provided. Next, a part of the silicon substrate is removed to form a ring hole and a silicon pillar surrounded by the silicon pillar. Then, a photosensitive material is disposed in the ring hole, wherein the photosensitive material is insulating. After that, the silicon pillar is removed, such that the ring hole forms a through hole and the photosensitive material covers a lateral wall of the through hole. Lastly, the conductive material is disposed in the through hole, wherein the outer surface of the conductive material is surrounded by the photosensitive material.

Abstract translation: 提供半导体结构，半导体结构的制造方法以及半导体封装。 制造半导体结构的方法包括以下步骤。 首先，提供硅基板。 接下来，去除硅衬底的一部分以形成由硅柱包围的环形孔和硅柱。 然后，感光材料设置在环形孔中，其中感光材料是绝缘的。 之后，去除硅柱，使得环孔形成通孔，并且感光材料覆盖通孔的侧壁。 最后，导电材料设置在通孔中，其中导电材料的外表面被感光材料包围。

公开(公告)号：US20090035932A1

公开(公告)日：2009-02-05

申请号：US12183140

申请日：2008-07-31

Applicant: Meng-Jen Wang

Inventor： Meng-Jen Wang

IPC: H01L21/4763

CPC classification number: H01L21/76898

Abstract: The present invention relates to a method for forming vias in a substrate, including the following steps: (a) providing a substrate having a first surface and a second surface; (b) forming a groove on the substrate; (c) filling the groove with a conductive metal; (d) removing part of the substrate which surrounds the conductive metal, wherein the conductive metal is maintained so as to form an accommodating space between the conductive metal and the substrate; (e) forming an insulating material in the accommodating space; and (f) removing part of the second surface of the substrate to expose the conductive metal and the insulating material. In this way, thicker insulating material can be formed in the accommodating space, and the thickness of the insulating material in the accommodating space is even.

Abstract translation: 本发明涉及一种在衬底中形成通孔的方法，包括以下步骤：（a）提供具有第一表面和第二表面的衬底; （b）在基板上形成凹槽; （c）用导电金属填充凹槽; （d）去除围绕所述导电金属的所述衬底的一部分，其中所述导电金属被保持以在所述导电金属和所述衬底之间形成容纳空间; （e）在容纳空间中形成绝缘材料; 和（f）去除衬底的第二表面的一部分以暴露导电金属和绝缘材料。 以这种方式，可以在容纳空间中形成更厚的绝缘材料，并且容纳空间中的绝缘材料的厚度是均匀的。

公开(公告)号：US07368806B2

公开(公告)日：2008-05-06

申请号：US11296489

申请日：2005-12-08

Applicant: Chien Liu ,  Meng-Jen Wang ,  Sheng-Tai Tsai

Inventor： Chien Liu ,  Meng-Jen Wang ,  Sheng-Tai Tsai

IPC: H01L23/495 ,  H01L23/48

CPC classification number: H01L24/16 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/4951 ,  H01L23/4952 ,  H01L24/81 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/16 ,  H01L2224/81136 ,  H01L2224/81139 ,  H01L2224/81141 ,  H01L2224/81193 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A flip chip package with an anti-floating structure includes a leadframe, a flip chip, and a plurality of solders. The leadframe includes a plurality of leads and a fastening part. At least one locking hole is formed on an upper surface of the fastening part. The flip chip includes an active surface, and at least one locking protrusion and a plurality of bumps formed on the active surface. The locking protrusion is correspondingly plugged into the locking hole to act as an anti-floating structure for the flip chip package. When the solders are used for connecting the bumps with the leads by reflowing, the anti-floating structure will prevent the flip chip from floating up, and the solders will not generate necking after reflowing.

Abstract translation: 具有防浮动结构的倒装芯片封装包括引线框，倒装芯片和多个焊料。 引线框架包括多个引线和紧固部件。 在紧固部的上表面上形成有至少一个锁定孔。 倒装芯片包括有源表面，以及形成在有源表面上的至少一个锁定突起和多个凸块。 锁定突起相应地插入到锁定孔中，以用作倒装芯片封装的防浮动结构。 当焊料用于通过回流连接凸起与引线时，反浮动结构将防止倒装芯片浮起，并且焊料在回流之后不会产生颈缩。

公开(公告)号：US20060244115A1

公开(公告)日：2006-11-02

申请号：US11313679

申请日：2005-12-22

Applicant: Chien Liu ,  Meng-Jen Wang

Inventor： Chien Liu ,  Meng-Jen Wang

IPC: H01L23/02

CPC classification number: H01L23/4951 ,  H01L23/49517 ,  H01L23/49548 ,  H01L23/49568 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2224/0401

Abstract: A chip package structure and a method for manufacturing the same are disclosed. The chip package structure comprises a carrier and a chip deposed on the carrier. The carrier comprises a heat-sinking pad, a plurality of pins, and at least two supporting bars, in which the heat-sinking pad has a carrying surface. The chip includes a plurality of bonding bumps flipped and connected to the heat-sinking pad, the pins, and the supporting bars of the carrier.

Abstract translation: 公开了一种芯片封装结构及其制造方法。 芯片封装结构包括载体和放置在载体上的芯片。 载体包括散热垫，多个销和至少两个支撑条，其中散热垫具有承载表面。 芯片包括翻转并连接到散热垫，引脚和载体的支撑杆的多个接合凸块。

公开(公告)号：US20050189633A1

公开(公告)日：2005-09-01

申请号：US10906536

申请日：2005-02-24

Applicant: Meng-Jen Wang ,  Chih-Ming Chung

Inventor： Meng-Jen Wang ,  Chih-Ming Chung

IPC: H01L21/56 ,  H01L23/16 ,  H01L23/28 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L21/563 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A chip package structure comprising a substrate, a chip, a plurality of bumps, some buffer material and some encapsulation is provided. The substrate has a first surface and a corresponding second surface. The chip has an active surface and a back surface. The bumps are disposed between the active surface of the chip and the first surface of the substrate. The buffer material is disposed on the back surface of the chip. The encapsulation is disposed over the first surface of the substrate to enclose the chip and the buffer material.

Abstract translation: 提供了包括衬底，芯片，多个凸块，一些缓冲材料和一些封装的芯片封装结构。 衬底具有第一表面和相应的第二表面。 芯片具有活性表面和背面。 凸块设置在芯片的有源表面和基板的第一表面之间。 缓冲材料设置在芯片的背面。 封装设置在衬底的第一表面上以包围芯片和缓冲材料。

公开(公告)号：US20050101053A1

公开(公告)日：2005-05-12

申请号：US10967910

申请日：2004-10-18

Applicant: Hsueh-Te Wang ,  Meng-Jen Wang ,  Chien Liu ,  Chi-Hao Chiu

Inventor： Hsueh-Te Wang ,  Meng-Jen Wang ,  Chien Liu ,  Chi-Hao Chiu

IPC: H01L23/31 ,  H01L23/495 ,  H01L21/48

CPC classification number: H01L23/49558 ,  H01L23/3114 ,  H01L23/49586 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2224/05599

Abstract: A quad flat flip chip packaging process and a leadframe therefor are provided. A sacrificial film is attached on the leads of the leadframe for limiting the extent of bumps when formed and saving the manufacturing cost. Besides, the sacrificial film can be removed from the leadframe after a reflow step. Thus, the delamination between the molding compound material and the leads can be prevented during the molding step.

Abstract translation: 提供了一种四平面倒装芯片封装工艺及其引线框架。 牺牲膜附着在引线框架的引线上，用于在形成时限制凸块的程度并节省制造成本。 此外，在回流步骤之后，牺牲膜可以从引线框架移除。 因此，可以在成型步骤期间防止模塑料和导线之间的分层。

公开(公告)号：US06856027B2

公开(公告)日：2005-02-15

申请号：US10820826

申请日：2004-04-09

Applicant: Meng-Jen Wang

Inventor： Meng-Jen Wang

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/02

CPC classification number: H01L24/49 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/4824 ,  H01L2224/49109 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/0401

Abstract: A multi-chips stacked package at least comprises a substrate, an upper chip, a lower chip, a plurality of electrically conductive wires and a plurality of conductive bumps. The upper chip is flip-chip bonded to the upper surface of the substrate; and the lower chip is accommodated in the opening and wire-bonded to the upper chip. Furthermore, the lower chip can be wire-bonded to the substrate via a plurality of another electrically conductive wires, which directly connect the lower chip and the substrate.

Abstract translation: 多芯片堆叠封装至少包括衬底，上芯片，下芯片，多个导电线和多个导电凸块。 上芯片倒装芯片结合到基板的上表面; 并且下部芯片容纳在开口中并且引线接合到上部芯片。 此外，下部芯片可以通过直接连接下部芯片和基板的多条另外的导电线进行引线接合到基板。