公开(公告)号：US07375435B2

公开(公告)日：2008-05-20

申请号：US10906536

申请日：2005-02-24

申请人： Meng-Jen Wang ,  Chih-Ming Chung

发明人： Meng-Jen Wang ,  Chih-Ming Chung

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/563 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A chip package structure comprising a substrate, a chip, a plurality of bumps, some buffer material and some encapsulation is provided. The substrate has a first surface and a corresponding second surface. The chip has an active surface and a back surface. The bumps are disposed between the active surface of the chip and the first surface of the substrate. The buffer material is disposed on the back surface of the chip. The encapsulation is disposed over the first surface of the substrate to enclose the chip and the buffer material.

摘要翻译： 提供了包括衬底，芯片，多个凸块，一些缓冲材料和一些封装的芯片封装结构。 衬底具有第一表面和相应的第二表面。 芯片具有活性表面和背面。 凸块设置在芯片的有源表面和基板的第一表面之间。 缓冲材料设置在芯片的背面。 封装设置在衬底的第一表面上以包围芯片和缓冲材料。

公开(公告)号：US20050189633A1

公开(公告)日：2005-09-01

申请号：US10906536

申请日：2005-02-24

申请人： Meng-Jen Wang ,  Chih-Ming Chung

发明人： Meng-Jen Wang ,  Chih-Ming Chung

IPC分类号： H01L21/56 ,  H01L23/16 ,  H01L23/28 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065

CPC分类号： H01L21/563 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A chip package structure comprising a substrate, a chip, a plurality of bumps, some buffer material and some encapsulation is provided. The substrate has a first surface and a corresponding second surface. The chip has an active surface and a back surface. The bumps are disposed between the active surface of the chip and the first surface of the substrate. The buffer material is disposed on the back surface of the chip. The encapsulation is disposed over the first surface of the substrate to enclose the chip and the buffer material.

摘要翻译： 提供了包括衬底，芯片，多个凸块，一些缓冲材料和一些封装的芯片封装结构。 衬底具有第一表面和相应的第二表面。 芯片具有活性表面和背面。 凸块设置在芯片的有源表面和基板的第一表面之间。 缓冲材料设置在芯片的背面。 封装设置在衬底的第一表面上以包围芯片和缓冲材料。

公开(公告)号：US08384204B2

公开(公告)日：2013-02-26

申请号：US12683613

申请日：2010-01-07

申请人： Chien Liu ,  Chih-Ming Chung

发明人： Chien Liu ,  Chih-Ming Chung

IPC分类号： H01L23/482 ,  H05K1/09

CPC分类号： H05K3/3452 ,  H01L21/563 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/498 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/05572 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48229 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/00014 ,  H05K3/3436 ,  H05K2201/10674 ,  H05K2201/2081 ,  H05K2203/0315 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A circuit carrier suitable for being connected with a bump is provided. The circuit carrier includes a substrate and at least one bonding pad. The substrate has a bonding pad disposed on a surface thereof for being connected with the bump. A brown-oxide layer is disposed on a surface of the bonding pad.

摘要翻译： 提供适于与凸块连接的电路载体。 电路载体包括衬底和至少一个接合焊盘。 衬底具有设置在其表面上用于与凸块连接的接合焊盘。 在接合焊盘的表面上设置有棕色氧化物层。

公开(公告)号：US07565737B2

公开(公告)日：2009-07-28

申请号：US11947791

申请日：2007-11-30

申请人： Chih-Ming Chung

发明人： Chih-Ming Chung

IPC分类号： H05K3/30

CPC分类号： H05K1/142 ,  H01L23/49833 ,  H01L2224/16 ,  H01L2924/09701 ,  H05K1/183 ,  H05K2201/0187 ,  H05K2201/10378 ,  H05K2201/10674 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49155

摘要： A package substrate for carrying a chip with a plurality of bumps thereon is provided. The package substrate includes a first substrate, and an interposer. The first substrate has a first circuit layer disposed on a surface thereof. The interposer includes a second substrate and a second circuit layer formed thereon. The second circuit layer comprises a plurality of bonding pads and traces. The traces are electrically connected to the corresponding bonding pads. Furthermore, the bonding pads are used for being connected to the bumps. The second circuit layer of the interposer is physically and electrically connected to the first circuit layer of the first substrate, and the second substrate and the first substrate are made of different materials.

摘要翻译： 提供了用于承载具有多个凸块的芯片的封装基板。 封装衬底包括第一衬底和中介层。 第一基板具有设置在其表面上的第一电路层。 插入器包括形成在其上的第二基板和第二电路层。 第二电路层包括多个接合焊盘和迹线。 迹线电连接到相应的焊盘。 此外，接合焊盘用于连接到凸块。 插入器的第二电路层物理地和电连接到第一衬底的第一电路层，第二衬底和第一衬底由不同的材料制成。

公开(公告)号：US20070052082A1

公开(公告)日：2007-03-08

申请号：US11306818

申请日：2006-01-12

申请人： Cheng-Yin Lee ,  Chih-Ming Chung ,  Wen-Pin Huang

发明人： Cheng-Yin Lee ,  Chih-Ming Chung ,  Wen-Pin Huang

IPC分类号： H01L23/02

CPC分类号： H01L25/03 ,  H01L23/3128 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2924/00

摘要： A multi-chip package structure including a carrier, a first chip having an active surface and a rear surface, multiple bumps, a second chip, multiple first bonding wires, a package unit disposed above the first chip, a spacer disposed between the package unit and the first chip, multiple second bonding wires, and an encapsulant is provided. The bumps are disposed between the active surface and the carrier to electrically connect the first chip and the carrier. The second chip is disposed on the rear surface of the first chip. The first bonding wires electrically connect the second chip and the carrier. The second bonding wires electrically connect the package unit and the carrier. The encapsulant is disposed on the carrier to encapsulate the first chip, the second chip, at least a portion of the package unit, the bumps, the spacer, the first bonding wires and the second bonding wires.

摘要翻译： 一种包括载体，具有活性表面的第一芯片和后表面的多芯片封装结构，多个凸点，第二芯片，多个第一接合线，设置在第一芯片上方的封装单元，设置在封装单元之间的间隔件 并提供第一芯片，多个第二接合线和密封剂。 凸起设置在有源表面和载体之间以电连接第一芯片和载体。 第二芯片设置在第一芯片的后表面上。 第一接合线将第二芯片和载体电连接。 第二接合线将封装单元和载体电连接。 密封剂设置在载体上以封装第一芯片，第二芯片，封装单元的至少一部分，凸块，间隔件，第一接合线和第二接合线。

公开(公告)号：US07327018B2

公开(公告)日：2008-02-05

申请号：US11163276

申请日：2005-10-12

申请人： Chih-Ming Chung

发明人： Chih-Ming Chung

IPC分类号： H01L23/02

CPC分类号： H05K1/142 ,  H01L23/49833 ,  H01L2224/16 ,  H01L2924/09701 ,  H05K1/183 ,  H05K2201/0187 ,  H05K2201/10378 ,  H05K2201/10674 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49155

摘要： A package substrate for carrying a chip with a plurality of bumps thereon is provided. The package substrate includes a first substrate, and an interposer. The first substrate has a first circuit layer disposed on a surface thereof. The interposer includes a second substrate and a second circuit layer formed thereon. The second circuit layer comprises a plurality of bonding pads and traces. The traces are electrically connected to the corresponding bonding pads. Furthermore, the bonding pads are used for being connected to the bumps. The second circuit layer of the interposer is physically and electrically connected to the first circuit layer of the first substrate, and the second substrate and the first substrate are made of different materials.

摘要翻译： 提供了用于承载具有多个凸块的芯片的封装基板。 封装衬底包括第一衬底和中介层。 第一基板具有设置在其表面上的第一电路层。 插入器包括形成在其上的第二基板和第二电路层。 第二电路层包括多个接合焊盘和迹线。 迹线电连接到相应的焊盘。 此外，接合焊盘用于连接到凸块。 插入器的第二电路层物理地和电连接到第一衬底的第一电路层，第二衬底和第一衬底由不同的材料制成。

公开(公告)号：US07163840B2

公开(公告)日：2007-01-16

申请号：US10709588

申请日：2004-05-17

申请人： Yu-Wen Chen ,  Chih-Ming Chung ,  Chi-Hao Chiu

发明人： Yu-Wen Chen ,  Chih-Ming Chung ,  Chi-Hao Chiu

IPC分类号： H01L21/48 ,  H01L21/50

CPC分类号： H01L24/28 ,  H01L21/563 ,  H01L23/36 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/73203 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/3025 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/05599

摘要： A flip chip package structure and manufacturing method thereof is provided. A chip is electrically connected to a substrate. A heat sink is attached to the backside of the chip. The heat sink has at least a through hole located at a peripheral region and laterally adjacent to the chip. A dispensing process is carried out to deliver an underfill material via the through hole such that the space between the chip and the substrate is filled. The underfill material also extends to cover a portion of the heat sink so that the heat sink and the substrate are connected together. The underfill material is cured to fix the heat sink, the substrate and the chip in position.

摘要翻译： 提供了一种倒装芯片封装结构及其制造方法。 芯片电连接到基板。 散热片连接到芯片的背面。 散热器至少具有位于周边区域并且横向邻近芯片的通孔。 进行分配处理以通过通孔输送底部填充材料，使得填充芯片和基板之间的空间。 底部填充材料还延伸以覆盖散热器的一部分，使得散热器和基板连接在一起。 固化底部填充材料以将散热器，基板和芯片固定就位。

公开(公告)号：US20060281223A1

公开(公告)日：2006-12-14

申请号：US11322676

申请日：2005-12-30

申请人： Chien Liu ,  Chih-Ming Chung

发明人： Chien Liu ,  Chih-Ming Chung

IPC分类号： H01L21/58

CPC分类号： H01L21/4846 ,  H01L21/563 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/32 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83051 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： The invention achieves the above-identified object by providing a packaging, comprising steps of: (a) providing an integrated circuit unit having an active surface, a plurality of bumps disposed thereon; (b) providing a substrate having a first surface and a second surface, a plurality of pads disposed on the first surface, a metal layer formed on the second surface; (c) forming an integrated circuit assembly by connecting the bumps and pads; and (d) forming a plurality of metallic pieces by etching the metal layer.

摘要翻译： 本发明通过提供一种包装来实现上述目的，包括以下步骤：（a）提供具有活性表面的集成电路单元，其上设置有多个凸块; （b）提供具有第一表面和第二表面的基底，设置在第一表面上的多个垫，形成在第二表面上的金属层; （c）通过连接凸起和焊盘形成集成电路组件; 和（d）通过蚀刻金属层形成多个金属片。

公开(公告)号：US20060088953A1

公开(公告)日：2006-04-27

申请号：US11136181

申请日：2005-05-24

申请人： Ming-Lun Ho ,  Chih-Ming Chung

发明人： Ming-Lun Ho ,  Chih-Ming Chung

IPC分类号： H01L21/50 ,  H01L21/44

CPC分类号： H01L24/81 ,  H01L21/563 ,  H01L24/16 ,  H01L24/29 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/83856 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H05K3/3436 ,  H01L2924/00 ,  H01L2224/0401

摘要： The present invention relates to a method for flip chip bonding by utilizing an interposer with embedded bumps. The method comprises (a) providing a first element having a first surface; (b) forming an interposer onto the first surface; (c) forming a plurality of openings on the interposer; (d) forming a plurality of bumps in the openings, wherein the height of the bumps is smaller than the depth of the openings; (e) providing a second element having a plurality of pre-solders; and (f) bonding the first surface onto the second element, so that the pre-solders are disposed in the openings and in contact with the bumps. As a result, the self-alignment between the pre-solders and the bumps can avoid the shift between the first element and the second element.

摘要翻译： 本发明涉及一种通过利用具有嵌入式凸块的插入件来进行倒装芯片接合的方法。 该方法包括（a）提供具有第一表面的第一元件; （b）在第一表面上形成插入件; （c）在所述插入件上形成多个开口; （d）在所述开口中形成多个凸起，其中所述凸块的高度小于所述开口的深度; （e）提供具有多个预焊料的第二元件; 和（f）将第一表面粘合到第二元件上，使得预焊料设置在开口中并与凸块接触。 结果，预焊料和凸块之间的自对准可以避免第一元件和第二元件之间的偏移。

公开(公告)号：US06150730A

公开(公告)日：2000-11-21

申请号：US349231

申请日：1999-07-08

申请人： Chih-Ming Chung ,  Kuo-Pin Yang ,  Jen-Kuang Fang ,  Su Tao

发明人： Chih-Ming Chung ,  Kuo-Pin Yang ,  Jen-Kuang Fang ,  Su Tao

IPC分类号： H01L23/495 ,  H01L23/498 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/4951 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/50 ,  H01L2924/14

摘要： A chip-scale semiconductor package mainly includes a semiconductor chip, a substrate and a package body. Said chip is attached onto said substrate by an adhesive layer. Said chip has a plurality of bonding pads formed thereon. Said adhesive layer has an aperture corresponding to the bonding pads of said chip such that the bonding pads can be exposed within an aperture. Said substrate has several through-holes respectively corresponding to the bonding pads of said chip and parts of the area around the edge of said chip for dispensing of encapsulant after the soldering of leads of said substrate to the bonding pads of said chip. The encapsulant dispensed into the through-holes can flow from the surface of said chip to the edge thereof. Said package body has one portion provided within the through-hole of said substrate and another portion provided around the edge of said chip whereby encapsulation process is accomplished without having to turn the whole semiconductor package device.

摘要翻译： 芯片级半导体封装主要包括半导体芯片，基板和封装体。 所述芯片通过粘合剂层附着在所述基板上。 所述芯片具有形成在其上的多个接合焊盘。 所述粘合剂层具有对应于所述芯片的焊盘的孔，使得焊盘可以暴露在孔内。 所述衬底具有分别对应于所述芯片的焊盘和所述芯片的边缘周围区域的部分的多个通孔，用于在将所述衬底的引线焊接到所述芯片的焊盘之后分配密封剂。 分配到通孔中的密封剂可以从所述芯片的表面流动到其边缘。 所述封装体具有设置在所述基板的通孔内的一部分和设置在所述芯片的边缘周围的另一部分，从而实现封装处理而不必转动整个半导体封装器件。