公开(公告)号：US20100237239A1

公开(公告)日：2010-09-23

申请号：US12223982

申请日：2007-02-14

申请人： Akira Noda ,  Yoshihisa Iwashita ,  Shu Nakamura ,  Hiroyuki Daido ,  Satoru Yamada

发明人： Akira Noda ,  Yoshihisa Iwashita ,  Shu Nakamura ,  Hiroyuki Daido ,  Satoru Yamada

IPC分类号： H01J49/40

CPC分类号： H01J49/40 ,  G01T1/20 ,  G01T1/29

摘要： In order to attain an object to realize an ion beam capable of (i) immediately determining energy of the ion beam to be generated, and (ii) measuring an ion beam in real time while carrying out laser irradiation, an ion beam detector (1) of the present invention includes a light conversion section (7) transmitting X-rays mixed in with ions (3) and converting the ions (3) to light; a light detection section (9) detecting, as an electric signal, the light converted from the ions (3) by the light converting section (7); a time-of-flight measurement section (10) measuring a time of flight for the ions (3) to reach the light conversion section (7); an electron removal section (5) removing electrons mixed in with the ions (3) and a light shielding section (6) shielding light mixed in with the ions (3), each of which is provided in an upstream of the light conversion section from which the ion beam comes to the light conversion section; and a curved section (8) between the light conversion section (7) and the light detection section (9), curved with respect to an optical axis of the ions (3) incident on the light conversion section (7).

摘要翻译： 为了实现能够（i）立即确定要产生的离子束的能量的离子束的实现，和（ii）在进行激光照射的同时实时测量离子束，离子束检测器（1） ）包括透射与离子（3）混合并将离子（3）转换成光的X射线的光转换部（7） 光检测部（9），通过光转换部（7）检测从离子（3）转换的光作为电信号; 测量离子（3）到达光转换部分（7）的飞行时间的飞行时间测量部分（10）; 去除与离子（3）混合的电子的电子去除部分（5）和屏蔽与离子（3）混合的光的遮光部分（6），每个离子（3）设置在光转换部分的上游 离子束到达光转换部分; 以及在光转换部（7）和光检测部（9）之间相对于入射在光转换部（7）上的离子（3）的光轴弯曲的弯曲部（8）。

公开(公告)号：US07392581B2

公开(公告)日：2008-07-01

申请号：US11681342

申请日：2007-03-02

申请人： Kan Sano ,  Satoru Yamada

发明人： Kan Sano ,  Satoru Yamada

IPC分类号： H01F7/06

CPC分类号： H01F27/027 ,  H01F27/255 ,  H01F27/2847 ,  H01F27/292 ,  H01F41/005 ,  H01F2017/046 ,  Y10T29/49021 ,  Y10T29/49032 ,  Y10T29/4905 ,  Y10T29/49071 ,  Y10T29/49073 ,  Y10T29/49146 ,  Y10T29/49171 ,  Y10T29/4922 ,  Y10T29/49222

摘要： A plate member includes a frame portion (51) provided in a state of coupling both one end portion and other end portion and mounting terminal portions (44) protruding from the one end portion and the other end portion of said frame portion (51) to approach each other, from which a PCB joint portions (46) to be a mounting portion to a PCB are formed by cutting and bending when manufacturing a magnetic element. Further, a winding number adjustment means (41), which is capable of selecting joint portions with ends of a coil and adjusting the winding number of the coil in accordance with the selection, protrudes from the one end portion and the other end portion to approach each other farther as compared to the mounting terminal portions (44).

摘要翻译： 板构件包括以一端部和另一端部连接的状态设置的框架部分（51），以及从所述框架部分（51）的一个端部部分和另一个端部部分伸出的安装端子部分（44）到 彼此接近，当制造磁性元件时，通过切割和弯曲来形成作为安装部分的PCB连接部分（46）。 此外，能够根据选择来选择线圈端部的接合部分和线圈的绕组数量的绕组数量调节装置（41）从一个端部部分和另一个端部部分接近 与安装端子部分（44）相比，彼此更远。

公开(公告)号：US20070242323A1

公开(公告)日：2007-10-18

申请号：US11727926

申请日：2007-03-29

申请人： Satoru Yamada

发明人： Satoru Yamada

IPC分类号： G03H1/02

CPC分类号： G03H1/02 ,  G03H2001/0264 ,  G03H2250/34 ,  G03H2260/12 ,  G11B7/0065 ,  G11B7/0938 ,  G11B7/1275 ,  G11B7/24044 ,  G11B7/245

摘要： Provided is a holographic recording composition comprising an imine compound having a pKa of 11 or more in water at 25° C., and, an acidic compound having a pKa of below 11 in water at 25° C. Preferably, the imine compound having a pKa of 11 or more in water at 25° C. is expressed by General Formula (1) below: in the General Formula (1), R1, R2 and R3, which may be identical or different each other, each represents an alkyl group, an aryl group, an amino group or an acyl group; the alkyl group, the aryl group, the amino group or the acyl group may further have a substituent.

摘要翻译： 本发明提供一种全息记录组合物，其包含在25℃下在水中pKa为11以上的亚胺化合物和在25℃下在水中pKa低于11的酸性化合物。优选地，具有 在25℃的水中的11K以上的pKa由下述通式（1）表示：在通式（1）中，R 1，R 2，和 R 3可以相同或不同，各自表示烷基，芳基，氨基或酰基; 烷基，芳基，氨基或酰基可以进一步具有取代基。

公开(公告)号：US20070099364A1

公开(公告)日：2007-05-03

申请号：US11586493

申请日：2006-10-26

申请人： Takuo Ohashi ,  Taishi Kubota ,  Toru Miyazaki ,  Shigetomi Michimata ,  Satoru Yamada

发明人： Takuo Ohashi ,  Taishi Kubota ,  Toru Miyazaki ,  Shigetomi Michimata ,  Satoru Yamada

IPC分类号： H01L21/8234 ,  H01L21/8242 ,  H01L21/336 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L27/10873 ,  H01L21/28061 ,  H01L21/28247 ,  H01L21/823828 ,  H01L21/823857

摘要： A method for forming a semiconductor device having a polymetal gate electrode includes the steps of forming a gate oxide film on a silicon substrate, forming a polysilicon film and a tungsten film on the gate oxide film, patterning the polysilicon film and tungsten film, and thermally oxidizing the polysilicon film in an oxidizing atmosphere including water and hydrogen at a substrate-surface temperature of 850 degrees C. and a water content of 7% to 20%.

摘要翻译： 一种形成具有多金属栅电极的半导体器件的方法包括以下步骤：在硅衬底上形成栅极氧化膜，在栅极氧化膜上形成多晶硅膜和钨膜，对多晶硅膜和钨膜进行构图， 在850℃的基板表面温度和7％〜20％的含水量下，在包括水和氢的氧化气氛中氧化多晶硅膜。

公开(公告)号：US07057243B2

公开(公告)日：2006-06-06

申请号：US10648883

申请日：2003-08-27

申请人： Satoru Yamada ,  Ryo Nagai ,  Kiyonori Oyu ,  Ryoichi Nakamura ,  Norikatsu Takaura

发明人： Satoru Yamada ,  Ryo Nagai ,  Kiyonori Oyu ,  Ryoichi Nakamura ,  Norikatsu Takaura

IPC分类号： H01L29/94

CPC分类号： H01L27/10891 ,  H01L21/28061 ,  H01L21/823842 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/4941 ,  H01L29/7833

摘要： In a semiconductor device of a polysilicon gate electrode structure having three or more different Fermi levels, a P type polysilicon having a lowest Fermi level is disposed on a first N type surface channel MOS transistor. A first N type polysilicon having a highest Fermi level is disposed on a second N type surface channel MOS transistor. A second N type polysilicon having an intermediate Fermi level between the highest and the lowest Fermi levels and doped with both an N type impurity and a P type impurity is disposed on a P channel MOS transistor.

摘要翻译： 在具有三个或更多个不同费米能级的多晶硅栅电极结构的半导体器件中，具有最低费米能级的P型多晶硅设置在第一N型表面沟道MOS晶体管上。 具有最高费米能级的第一N型多晶硅被布置在第二N型表面沟道MOS晶体管上。 具有最高和最低费米能级之间的中间费米能级并且掺杂有N型杂质和P型杂质的第二N型多晶硅设置在P沟道MOS晶体管上。

公开(公告)号：US20050150773A1

公开(公告)日：2005-07-14

申请号：US10999926

申请日：2004-12-01

申请人： Satoru Yamada ,  Noboru Toyama ,  Ryo Hayashi ,  Yuichi Sonoda ,  Tomonori Nishimoto ,  Masumitsu Iwata ,  Yusuke Miyamoto ,  Takaharu Kondo

发明人： Satoru Yamada ,  Noboru Toyama ,  Ryo Hayashi ,  Yuichi Sonoda ,  Tomonori Nishimoto ,  Masumitsu Iwata ,  Yusuke Miyamoto ,  Takaharu Kondo

IPC分类号： C25D9/08 ,  C23C28/00 ,  C23C28/04 ,  C25D5/34 ,  C25D5/48 ,  H01L21/288 ,  H01L31/04

CPC分类号： C25D5/48 ,  C23C28/00 ,  C25D5/34

摘要： A method for forming a deposition film from an aqueous solution by electrochemical reaction includes the steps of: forming the targeted deposition film under primary deposition conditions; replacing at least part of members in contact with the solution or removing deposit on surfaces of the members; and depositing a film under secondary deposition conditions. These steps are performed in that order. Then, the deposition film is formed again under the primary deposition conditions. In the method, the resulting deposition film exhibits desired characteristics even after maintenance of the deposition apparatus.

摘要翻译： 通过电化学反应从水溶液形成沉积膜的方法包括以下步骤：在初始沉积条件下形成目标沉积膜; 替换至少部分与溶液接触的构件或去除构件表面上的沉积物; 并在二次沉积条件下沉积薄膜。 这些步骤按照顺序执行。 然后，在初始沉积条件下再次形成沉积膜。 在该方法中，即使在保存沉积设备之后，所得到的沉积膜也显示出期望的特性。

公开(公告)号：US20050040452A1

公开(公告)日：2005-02-24

申请号：US10959634

申请日：2004-10-07

申请人： Yoshitaka Nakamura ,  Tsuyoshi Tamaru ,  Naoki Fukuda ,  Hidekazu Goto ,  Isamu Asano ,  Hideo Aoki ,  Keizo Kawakita ,  Satoru Yamada ,  Katsuhiko Tanaka ,  Hiroshi Sakuma ,  Masayoshi Hirasawa

发明人： Yoshitaka Nakamura ,  Tsuyoshi Tamaru ,  Naoki Fukuda ,  Hidekazu Goto ,  Isamu Asano ,  Hideo Aoki ,  Keizo Kawakita ,  Satoru Yamada ,  Katsuhiko Tanaka ,  Hiroshi Sakuma ,  Masayoshi Hirasawa

IPC分类号： H01L21/8242 ,  H01L23/522 ,  H01L29/76

CPC分类号： H01L27/10852 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： The semiconductor device is formed according to the following steps. A TiN film 71 and a W film 72 are deposited on a silicon oxide film 64 including the inside of a via-hole 66 by the CVD method and thereafter, the W film 72 and TiN film 71 on the silicon oxide film 64 are etched back to leave only the inside of the via-hole 66 and form a plug 73. Then, a TiN film 74, Al-alloy film 75, and Ti film 76 are deposited on the silicon oxide film 64 including the surface of the plug 73 by the sputtering method and thereafter, the Ti film 76, Al-alloy film 75, and TiN film 74 are patterned to form second-layer wirings 77 and 78.

公开(公告)号：US06809364B2

公开(公告)日：2004-10-26

申请号：US10630695

申请日：2003-07-31

申请人： Hideyuki Matsuoka ,  Satoru Yamada ,  Isamu Asano ,  Ryo Nagai ,  Tomonori Sekiguchi ,  Riichiro Takemura

发明人： Hideyuki Matsuoka ,  Satoru Yamada ,  Isamu Asano ,  Ryo Nagai ,  Tomonori Sekiguchi ,  Riichiro Takemura

IPC分类号： H01L27108

CPC分类号： H01L27/10855 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/10897 ,  Y10S257/906 ,  Y10S257/907 ,  Y10S257/908

摘要： A DRAM of an open bit line structure has a cell area smaller than that of a DRAM of a folded bit line structure and is susceptible to noise. A conventional DRAM of an open bit line structure has a large bit line capacitance and is susceptible to noise or has a large cell area. There has been no DRAM of an open bit line structure having a small bit line capacitance, unsusceptible to noise and having a small cell area. The present invention forms capacitor lower electrode plug holes not aligned with bit lines to reduce bit line capacitance. Bit lines are formed in a small width, capacitor lower electrode plugs are dislocated from positions corresponding to the centers of the bit lines in directions away from the bit lines and the contacts are formed in a reduced diameter to avoid increasing the cell area. Thus a semiconductor storage device of an open bit line structure resistant to noise and having a small cell area is provided.

公开(公告)号：US06734060B2

公开(公告)日：2004-05-11

申请号：US09208879

申请日：1998-12-10

申请人： Yoshitaka Nakamura ,  Isamu Asano ,  Keizou Kawakita ,  Satoru Yamada

发明人： Yoshitaka Nakamura ,  Isamu Asano ,  Keizou Kawakita ,  Satoru Yamada

IPC分类号： H01L218242

CPC分类号： H01L27/10894 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5226 ,  H01L27/10814 ,  H01L27/10882 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a peripheral circuit region of a DRAM, two connection holes 17a, 17b for connecting a first layer line 14 and a second layer line 26 electrically are opened separately in two processes. After forming the connection holes 17a and 17b, plugs 18a and 215a are formed in the connection holes 17a and 17b, respectively.

摘要翻译： 在DRAM的外围电路区域中，用于连接第一层布线14和第二层布线26的两个连接孔17a，17b在两个工序中单独打开。 在形成连接孔17a和17b之后，分别在连接孔17a和17b中形成插头18a和215a。

公开(公告)号：US06664597B2

公开(公告)日：2003-12-16

申请号：US10025561

申请日：2001-12-26

申请人： Yoshifumi Takeyama ,  Ichiro Kataoka ,  Satoru Yamada

发明人： Yoshifumi Takeyama ,  Ichiro Kataoka ,  Satoru Yamada

IPC分类号： H01L2701

CPC分类号： H01L31/052 ,  H01L31/02008 ,  H01L31/0516 ,  Y02E10/52

摘要： A retaining substrate for mounting a semiconductor element thereon, having a circuit pattern for said semiconductor element, characterized in that said substrate comprises an insulative material, said substrate has a surface configuration having a cross section comprising (a) an uneven shaped portion and (b) a concave shaped portion which are arranged in tandem wherein a surface of said uneven shaped portion (a) makes a bottom face of said concave portion (b), and said uneven shaped portion (a) has a structure in that (a-i) an insulative convex shaped portion and (a-ii) an insulative concave shaped portion are alternately arranged so as to neighbor with each other, and said circuit pattern is provided in said concave shaped portion (a-ii) of said uneven shaped portion (a).