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    Semiconductor device and method for manufacturing the same
    51.
    发明授权
    Semiconductor device and method for manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US09153646B2

    公开(公告)日：2015-10-06

    申请号：US13795339

    申请日：2013-03-12

    申请人： Kabushiki Kaisha Toshiba

    发明人： Tatsuo Shimizu ,  Takashi Shinohe

    IPC分类号： H01L29/78 ,  H01L29/16 ,  H01L29/66 ,  H01L29/10 ,  H01L29/167 ,  H01L21/04 ,  H01L29/32 ,  H01L29/34 ,  H01L29/739 ,  H01L29/94 ,  H01L29/08

    CPC分类号： H01L29/1608 ,  H01L21/049 ,  H01L29/04 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/105 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/32 ,  H01L29/34 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/7391 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/7805 ,  H01L29/94

    摘要： According to one embodiment, a semiconductor device includes a structural body, an insulating film, and a control electrode. The structural body has a first surface, and includes a first semiconductor region including silicon carbide of a first conductivity type, a second semiconductor region including silicon carbide of a second conductivity type, and a third semiconductor region including silicon carbide of the first conductivity type. The structural body has a portion in which the first semiconductor region, the second semiconductor region, and the third semiconductor region are arranged in this order in a first direction along the first surface. The insulating film is provided on the first surface of the structural body. The control electrode is provided on the insulating film. The structural body has a buried region provided between the second semiconductor region and the first surface. The buried region is doped with a group V element.

    摘要翻译： 根据一个实施例，半导体器件包括结构体，绝缘膜和控制电极。 结构体具有第一表面，并且包括第一半导体区域，其包括第一导电类型的碳化硅，第二半导体区域，包括第二导电类型的碳化硅，第三半导体区域包括第一导电类型的碳化硅。 结构体具有第一半导体区域，第二半导体区域和第三半导体区域沿着第一表面沿第一方向依次布置的部分。 绝缘膜设置在结构体的第一表面上。 控制电极设置在绝缘膜上。 结构体具有设置在第二半导体区域和第一表面之间的掩埋区域。 掩埋区域掺杂有V族元素。

    Semiconductor device having a plurality of transistors with different crystal face
    54.
    发明授权
    Semiconductor device having a plurality of transistors with different crystal face 有权
    具有多个具有不同晶面的晶体管的半导体器件

    公开(公告)号：US09018636B2

    公开(公告)日：2015-04-28

    申请号：US13782318

    申请日：2013-03-01

    申请人： Kabushiki Kaisha Toshiba

    发明人： Ryosuke Iijima ,  Yukio Nakabayashi ,  Takashi Shinohe

    IPC分类号： H01L29/04 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L21/82 ,  H01L27/06 ,  H01L29/16

    CPC分类号： H01L29/045 ,  H01L21/02433 ,  H01L21/8213 ,  H01L21/8238 ,  H01L27/0605 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0657 ,  H01L29/1608

    摘要： According to one embodiment, a semiconductor device includes a first and a second transistor. The first transistor includes a first and a second region of a first conductivity type and a third region of a second conductivity type. The first region is disposed along a first crystal face of a silicon carbide region. The silicon carbide region has the first crystal face and a second crystal face. The second and the third region are disposed along the first face. The third region is provided between the first and the second region. The second transistor includes a fourth and fifth region of the second type and a sixth region of the first type. The fourth, the fifth and the sixth region are disposed along the second face of the silicon carbide region. The sixth region is provided between the fourth and the fifth region.

    摘要翻译： 根据一个实施例，半导体器件包括第一和第二晶体管。 第一晶体管包括第一导电类型的第一和第二区域以及第二导电类型的第三区域。 第一区域沿着碳化硅区域的第一晶面设置。 碳化硅区域具有第一晶面和第二晶面。 第二和第三区域沿着第一面设置。 第三区域设置在第一和第二区域之间。 第二晶体管包括第二类型的第四和第五区域以及第一类型的第六区域。 第四，第五和第六区域沿着碳化硅区域的第二面设置。 第六区域设置在第四和第五区域之间。

    Semiconductor device
    55.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US09012923B2

    公开(公告)日：2015-04-21

    申请号：US14448345

    申请日：2014-07-31

    申请人： Kabushiki Kaisha Toshiba

    发明人： Johji Nishio ,  Tatsuo Shimizu ,  Ryosuke Iijima ,  Chiharu Ota ,  Takashi Shinohe

    IPC分类号： H01L29/15 ,  H01L29/36 ,  H01L29/16 ,  H01L29/167 ,  H01L29/78

    CPC分类号： H01L29/36 ,  H01L21/046 ,  H01L29/1029 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/66068 ,  H01L29/7395 ,  H01L29/7802

    摘要： A semiconductor device of an embodiment includes: an n-type first SiC epitaxial layer; a p-type second SiC epitaxial layer on the first SiC epitaxial layer containing a p-type impurity and an n-type impurity, the p-type impurity being an element A, the n-type impurity being an element D, the element A and the element D forming a combination of Al, Ga, or In and N, and/or a combination of B and P, the ratio of the concentration of the element D to the element A being higher than 0.33 but lower than 1.0; a surface region at the surface of the second SiC epitaxial layer containing the element A at a lower concentration than in the second SiC epitaxial layer, the ratio being higher than in the second SiC epitaxial layer; n-type first and second SiC regions; a gate insulating film; a gate electrode; a first electrode; and a second electrode.

    摘要翻译： 实施例的半导体器件包括：n型第一SiC外延层; 在包含p型杂质和n型杂质的第一SiC外延层上的p型第二SiC外延层，p型杂质为元素A，n型杂质为元素D，元素A 并且形成Al，Ga或In和N的组合的元素D和/或B和P的组合，元素D与元素A的浓度比率高于0.33但低于1.0; 所述第二SiC外延层的表面的表面区域含有比所述第二SiC外延层低的浓度的所述元素A，所述比率高于所述第二SiC外延层中的比率; n型第一和第二SiC区域; 栅极绝缘膜; 栅电极; 第一电极; 和第二电极。

    SIC EPITAXIAL WAFER AND SEMICONDUCTOR DEVICE
    56.
    发明申请
    SIC EPITAXIAL WAFER AND SEMICONDUCTOR DEVICE 有权
    SiC外延晶体管和半导体器件

    公开(公告)号：US20140284619A1

    公开(公告)日：2014-09-25

    申请号：US14205792

    申请日：2014-03-12

    申请人： Kabushiki Kaisha Toshiba

    发明人： Johji NISHIO ,  Tatsuo Shimizu ,  Chiharu Ota ,  Takashi Shinohe

    IPC分类号： H01L29/16

    CPC分类号： H01L29/1608 ,  C30B29/36 ,  H01L21/02378 ,  H01L21/02447 ,  H01L21/02529 ,  H01L21/02576 ,  H01L21/02579 ,  H01L29/045 ,  H01L29/66068 ,  H01L29/7827

    摘要： An SiC epitaxial wafer of an embodiment includes, an SiC substrate, and a p-type first SiC epitaxial layer that is formed on the SiC substrate and contains a p-type impurity and an n-type impurity. An element A and an element D being a combination of Al (aluminum), Ga (gallium), or In (indium) and N (nitrogen), and/or a combination of B (boron) and P (phosphorus) when the p-type impurity is the element A and the n-type impurity is the element D. The ratio of the concentration of the element D to the concentration of the element A in the combination(s) is higher than 0.33 but lower than 1.0.

    摘要翻译： 实施方案的SiC外延晶片包括SiC衬底和形成在SiC衬底上并包含p型杂质和n型杂质的p型第一SiC外延层。 元素A和元素D是Al（铝），Ga（镓）或In（铟）和N（氮）的组合，和/或B（硼）和P（磷）的组合，当p 型杂质是元素A，n型杂质是元素D.组合（D）中元素D的浓度与元素A的浓度之比高于0.33但低于1.0。

    Semiconductor device
    57.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US09837488B2

    公开(公告)日：2017-12-05

    申请号：US14612471

    申请日：2015-02-03

    申请人： Kabushiki Kaisha Toshiba

    发明人： Hisashi Saito ,  Masahiko Kuraguchi ,  Takashi Shinohe

    IPC分类号： H01L29/778 ,  H01L29/205 ,  H01L29/20 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/15

    CPC分类号： H01L29/0634 ,  H01L29/0847 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/7786

    摘要： According to one embodiment, a semiconductor device includes a first semiconductor layer; a second semiconductor layer having a larger band gap than the first semiconductor layer; a third semiconductor layer having a smaller band gap than the second semiconductor layer; a first electrode being in contact with the third semiconductor layer; a second electrode being in contact with the third semiconductor layer; and a third electrode provided between the third semiconductor layer in contact with the first electrode, the second semiconductor layer directly below the first electrode, and the first semiconductor layer directly below the first electrode, and the third semiconductor layer in contact with the second electrode, the second semiconductor layer directly below the second electrode, and the first semiconductor layer directly below the second electrode, being in contact with the third semiconductor layer, the second semiconductor layer, and the first semiconductor layer via insulating film.