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    VOLTAGE CONTROLLED OSCILLATOR
    51.
    发明申请
    VOLTAGE CONTROLLED OSCILLATOR 失效
    电压控制振荡器

    公开(公告)号：US20070209176A1

    公开(公告)日：2007-09-13

    申请号：US11741473

    申请日：2007-04-27

    Applicant: Takashi KAWAKUBO ,  Kazuhide Abe ,  Mayumi Morizuka

    Inventor： Takashi KAWAKUBO ,  Kazuhide Abe ,  Mayumi Morizuka

    IPC: H04R17/00 ,  H05K3/10

    CPC classification number: H03H9/173 ,  H03B5/326 ,  H03B5/366 ,  H03H9/0542 ,  H03H2009/02204 ,  Y10T29/42 ,  Y10T29/43 ,  Y10T29/49005 ,  Y10T29/49155

    Abstract: The present invention provides a voltage controlled oscillator comprising an thin film BAW resonator and a variable capacitor element. The thin film BAW resonator includes an anchor section formed on a Si substrate, a lower electrode supported on the anchor section and positioned to face the Si substrate, a first piezoelectric film formed on the lower electrode, and an upper electrode formed on the first piezoelectric film. On the other hand, the variable capacitor element includes a stationary electrode formed on a Si substrate, an anchor section formed on the Si substrate, a first electrode supported on the anchor section and positioned to face the Si substrate, a second piezoelectric film formed on the first electrode, and a second electrode formed on the second piezoelectric film.

    Abstract translation: 本发明提供一种包括薄膜BAW谐振器和可变电容器元件的压控振荡器。 薄膜BAW谐振器包括形成在Si衬底上的锚定部分，支撑在锚固部分上并定位成面对Si衬底的下电极，形成在下电极上的第一压电膜，以及形成在第一压电 电影。 另一方面，可变电容器元件包括形成在Si衬底上的固定电极，形成在Si衬底上的锚定部分，支撑在锚定部分上并且定位成面对Si衬底的第一电极，形成在第二压电膜上的第二压电膜 第一电极和形成在第二压电膜上的第二电极。

    Voltage controlled oscillator
    52.
    发明授权
    Voltage controlled oscillator 失效
    压控振荡器

    公开(公告)号：US07211933B2

    公开(公告)日：2007-05-01

    申请号：US10935264

    申请日：2004-09-08

    Applicant: Takashi Kawakubo ,  Kazuhide Abe ,  Mayumi Morizuka

    Inventor： Takashi Kawakubo ,  Kazuhide Abe ,  Mayumi Morizuka

    IPC: H01L41/08

    CPC classification number: H03H9/173 ,  H03B5/326 ,  H03B5/366 ,  H03H9/0542 ,  H03H2009/02204 ,  Y10T29/42 ,  Y10T29/43 ,  Y10T29/49005 ,  Y10T29/49155

    Abstract: The present invention provides a voltage controlled oscillator comprising an thin film BAW resonator and a variable capacitor element. The thin film BAW resonator includes an anchor section formed on a Si substrate, a lower electrode supported on the anchor section and positioned to face the Si substrate, a first piezoelectric film formed on the lower electrode, and an upper electrode formed on the first piezoelectric film. On the other hand, the variable capacitor element includes a stationary electrode formed on a Si substrate, an anchor section formed on the Si substrate, a first electrode supported on the anchor section and positioned to face the Si substrate, a second piezoelectric film formed on the first electrode, and a second electrode formed on the second piezoelectric film.

    Abstract translation: 本发明提供一种包括薄膜BAW谐振器和可变电容器元件的压控振荡器。 薄膜BAW谐振器包括形成在Si衬底上的锚定部分，支撑在锚固部分上并定位成面对Si衬底的下电极，形成在下电极上的第一压电膜，以及形成在第一压电 电影。 另一方面，可变电容器元件包括形成在Si衬底上的固定电极，形成在Si衬底上的锚定部分，支撑在锚定部分上并且定位成面对Si衬底的第一电极，形成在第二压电膜上的第二压电膜 第一电极和形成在第二压电膜上的第二电极。

    Tunable filter and portable telephone
    54.
    发明授权
    Tunable filter and portable telephone 失效
    可调滤波器和便携式电话

    公开(公告)号：US07135940B2

    公开(公告)日：2006-11-14

    申请号：US11039872

    申请日：2005-01-24

    Applicant: Takashi Kawakubo ,  Ryoichi Ohara ,  Kazuhide Abe ,  Hiroshi Yoshida ,  Hiroshi Tsurumi

    Inventor： Takashi Kawakubo ,  Ryoichi Ohara ,  Kazuhide Abe ,  Hiroshi Yoshida ,  Hiroshi Tsurumi

    IPC: H03H21/00 ,  H03H9/54 ,  H03H9/64

    CPC classification number: H03J3/08 ,  H03H9/542 ,  H03H9/605 ,  H03H2210/012 ,  H03H2210/015 ,  H03J1/0008

    Abstract: A tunable filter has a plurality of variable capacitors and a plurality of inductor elements, each being formed on a common substrate, a filter circuit formed by using at least a portion of the plurality of variable capacitors and a portion of the plurality of inductor elements, a monitor circuit formed by using at least a portion of the plurality of variable capacitors and a portion of the plurality of inductor elements, a detecting circuit which detects a prescribed circuit constant of the monitor circuit, a storage which stores information relating to a reference circuit constant of the monitor circuit, and a capacitance control circuit which controls capacitance of the variable capacitors in the monitor circuit and capacitance of the variable capacitors in the filter circuit, based on a result detected by the detecting circuit and information stored in the storage.

    Abstract translation: 可调谐滤波器具有多个可变电容器和多个电感器元件，每个电感器元件形成在公共基板上，通过使用多个可变电容器的至少一部分和多个电感器元件的一部分形成的滤波器电路， 通过使用多个可变电容器的至少一部分和多个电感器元件的一部分形成的监视电路，检测监视电路的规定电路常数的检测电路，存储与参考电路有关的信息的存储器 基于由检测电路检测的结果和存储在存储器中的信息，控制监视电路中的可变电容器的电容和滤波器电路中的可变电容器的电容的电容控制电路。

    Ferroelectric memory device and method of manufacture of same
    55.
    发明申请
    Ferroelectric memory device and method of manufacture of same 有权
    铁电存储器件及其制造方法

    公开(公告)号：US20060226457A1

    公开(公告)日：2006-10-12

    申请号：US11393830

    申请日：2006-03-31

    Applicant: Kazuhide Abe

    Inventor： Kazuhide Abe

    IPC: H01L29/94

    CPC classification number: H01L27/11507 ,  H01L27/105 ,  H01L27/11502 ,  H01L27/11509 ,  H01L28/57 ,  H01L28/65

    Abstract: A ferroelectric memory device has a lower insulating film (first insulating film) formed on a semiconductor substrate. A ferroelectric capacitor structure is formed on the lower insulating film. The ferroelectric capacitor structure is created by layering in order a lower electrode, ferroelectric layer and upper electrode. The ferroelectric memory device also has an upper insulating film (fifth insulating film) which covers the ferroelectric capacitor structure. A wiring layer is formed over the upper insulating film. An aluminum oxide film of thickness 5 to 50 nm is formed so as to cover the wiring layer and upper insulating film.

    Abstract translation: 铁电存储器件具有形成在半导体衬底上的下绝缘膜（第一绝缘膜）。 在下绝缘膜上形成铁电电容器结构。 铁电电容器结构通过按照下电极，铁电层和上电极的分层来形成。 铁电存储器件还具有覆盖铁电体电容器结构的上绝缘膜（第五绝缘膜）。 在上绝缘膜上形成布线层。 形成厚度为5〜50nm的氧化铝膜，以覆盖布线层和上绝缘膜。

    Production method for wiring structure of semiconductor device
    56.
    发明申请
    Production method for wiring structure of semiconductor device 有权
    半导体器件布线结构的生产方法

    公开(公告)号：US20060014380A1

    公开(公告)日：2006-01-19

    申请号：US11230525

    申请日：2005-09-21

    Applicant: Kazuhide Abe

    Inventor： Kazuhide Abe

    IPC: H01L21/4763

    CPC classification number: H01L23/53295 ,  H01L21/2885 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76885 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: In a wiring structure of a semiconductor device, dielectric tolerance of the wiring is improved by preventing diffusion of the wiring material. The wiring structure of the semiconductor device includes a first insulating film having plural grooves, plural wiring films formed protrusively above tops of the first insulating film among the grooves, plural barrier films formed on bottoms of the wiring films and up to a higher position than the tops on sides of the wiring films, first cap films comprising metal films formed on tops of the wiring films, and a second cap film formed on at least respective sides of the first cap films and the barrier films.

    Abstract translation: 在半导体器件的布线结构中，通过防止布线材料的扩散，提高布线的电介质公差。 半导体器件的布线结构包括具有多个沟槽的第一绝缘膜，多个布线膜，突出地形成在沟槽中的第一绝缘膜的顶部之上，多个阻挡膜形成在布线膜的底部上方，高于 布线膜侧面的顶部，包含形成在布线膜的顶部的金属膜的第一盖膜，以及形成在第一盖膜和阻挡膜的至少两侧的第二盖膜。

    Wiring structure of semiconductor device and production method of the device
    57.
    发明授权
    Wiring structure of semiconductor device and production method of the device 有权
    半导体器件的接线结构及器件的制造方法

    公开(公告)号：US06969911B2

    公开(公告)日：2005-11-29

    申请号：US10760457

    申请日：2004-01-21

    Applicant: Kazuhide Abe

    Inventor： Kazuhide Abe

    IPC: H01L21/288 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/48 ,  H01L23/52 ,  H01L23/532 ,  H01L29/40

    CPC classification number: H01L23/53295 ,  H01L21/2885 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76885 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: In a wiring structure of a semiconductor device, dielectric tolerance of the wiring is improved by preventing diffusion of the wiring material. The wiring structure of the semiconductor device includes a first insulating film having plural grooves, plural wiring films formed protrusively above tops of the first insulating film among the grooves, plural barrier films formed on bottoms of the wiring films and up to a higher position than the tops on sides of the wiring films, first cap films including metal films formed on tops of the wiring films, and a second cap film formed on at least respective sides of the first cap films and the barrier films.

    Abstract translation: 在半导体器件的布线结构中，通过防止布线材料的扩散，提高布线的电介质公差。 半导体器件的布线结构包括具有多个沟槽的第一绝缘膜，多个布线膜，突出地形成在沟槽中的第一绝缘膜的顶部之上，多个阻挡膜形成在布线膜的底部上方，高于 在布线膜的两侧的顶部，包括形成在布线膜的顶部的金属膜的第一盖膜以及形成在第一盖膜和阻挡膜的至少各个侧面上的第二盖膜。

    Method of forming buried wiring in semiconductor device
    58.
    发明授权
    Method of forming buried wiring in semiconductor device 失效
    在半导体器件中形成掩埋布线的方法

    公开(公告)号：US06967157B2

    公开(公告)日：2005-11-22

    申请号：US11109634

    申请日：2005-04-20

    Applicant: Kazuhide Abe

    Inventor： Kazuhide Abe

    IPC: H01L21/3205 ,  H01L21/302 ,  H01L21/304 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/768

    CPC classification number: H01L21/7685 ,  H01L21/7684 ,  H01L21/76867

    Abstract: A method of forming buried wiring, includes the steps of forming an insulating layer having a trench on a semiconductor substrate; forming a conductive layer mainly composed of copper on the insulating layer in such a manner that the trench is filled with the conductive layer; removing an oxide layer generated in a surface of the conductive layer by oxidation; forming a cap layer made of a material having less mechanical strength than the oxide layer, on the conductive layer; and removing the cap layer and a part of the conductive layer by chemical mechanical polishing in such a manner that the conductive layer is left in the trench.

    Abstract translation: 一种形成掩埋布线的方法包括以下步骤：在半导体衬底上形成具有沟槽的绝缘层; 在所述绝缘层上形成主要由铜构成的导电层，以使所述沟槽填充有所述导电层; 通过氧化去除在导电层的表面中产生的氧化物层; 在所述导电层上形成由具有比所述氧化物层更小的机械强度的材料制成的盖层; 并且通过化学机械抛光以导电层留在沟槽中的方式去除覆盖层和导电层的一部分。

    Method of forming buried wiring in semiconductor device
    59.
    发明授权
    Method of forming buried wiring in semiconductor device 失效

    公开(公告)号：US06903020B2

    公开(公告)日：2005-06-07

    申请号：US10765155

    申请日：2004-01-28

    Applicant: Kazuhide Abe

    Inventor： Kazuhide Abe

    IPC: H01L21/3205 ,  H01L21/302 ,  H01L21/304 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/768

    CPC classification number: H01L21/7685 ,  H01L21/7684 ,  H01L21/76867

    Abstract: A method of forming buried wiring, includes the steps of forming an insulating layer having a trench on a semiconductor substrate; forming a conductive layer mainly composed of copper on the insulating layer in such a manner that the trench is filled with the conductive layer; removing an oxide layer generated in a surface of the conductive layer by oxidation; forming a cap layer made of a material having less mechanical strength than the oxide layer, on the conductive layer; and removing the cap layer and a part of the conductive layer by chemical mechanical polishing in such a manner that the conductive layer is left in the trench.

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