公开(公告)号：US20070210364A1

公开(公告)日：2007-09-13

申请号：US11547904

申请日：2005-04-21

申请人： Kiyoshi Kato ,  Yutaka Shionoiri

发明人： Kiyoshi Kato ,  Yutaka Shionoiri

IPC分类号： H01L27/108

CPC分类号： H01L27/1266 ,  G02F1/136213 ,  H01L21/288 ,  H01L21/32051 ,  H01L21/76801 ,  H01L21/76829 ,  H01L21/76838 ,  H01L27/0811 ,  H01L27/10805 ,  H01L27/1214 ,  H01L27/13 ,  H01L29/04 ,  H01L29/78675

摘要： A capacitor capable of functioning as a capacitor even when an AC voltage is applied thereto is provided without increasing the manufacturing steps of a semiconductor device. A transistor is used as a MOS capacitor where a pair of impurity regions formed on opposite sides of a channel formation region are each doped with impurities of different conductivity so as to be used as a source region or a drain region. Specifically, assuming that an impurity region that is doped with N-type impurities is referred to as an N-type region while an impurity region that is doped with P-type impurities is referred to as a P-type region, a transistor is provided where a channel formation region is interposed between the N-type region and the P-type region, which is used as a MOS capacitor.

摘要翻译： 在不增加半导体器件的制造步骤的情况下，即使在施加交流电压的情况下，也可以提供能够作为电容器起作用的电容器。 晶体管用作MOS电容器，其中形成在沟道形成区域的相对侧上的一对杂质区域各自掺杂有不同导电性的杂质，以便用作源极区域或漏极区域。 具体地说，假定掺杂有N型杂质的杂质区域称为N型区域，而掺杂有P型杂质的杂质区域称为P型区域，则提供晶体管 其中沟道形成区域被插入在用作MOS电容器的N型区域和P型区域之间。

公开(公告)号：US20070076515A1

公开(公告)日：2007-04-05

申请号：US11607053

申请日：2006-12-01

申请人： Yutaka Shionoiri ,  Tomoaki Atsumi ,  Kiyoshi Kato

发明人： Yutaka Shionoiri ,  Tomoaki Atsumi ,  Kiyoshi Kato

IPC分类号： G11C8/00

CPC分类号： G11C7/1096 ,  G11C7/1078 ,  G11C7/12 ,  G11C11/4094 ,  G11C17/12

摘要： According to the invention, mounting area is decreased and yield is improved by decreasing the number of elements, and a memory with less burden on peripheral circuitry and a driving method thereof are provided. The invention comprises a memory cell including a memory element in a region where a bit line and a word line cross with an insulator interposed between them, a column decoder, and a selector including a clocked inverter. An input node of the clocked inverter is connected to the bit line while an output node is connected to a data line. Among a plurality of transistors connected in series which form the clocked inverter, a gate of a P-type transistor of which source or drain is connected to a power source on the high potential side VDD and a gate of an N-type transistor of which source or drain is connected to a power source on the low potential side VSS are connected to the column decoder.

摘要翻译： 根据本发明，通过减少元件的数量来减小安装面积并提高产量，并且提供了对外围电路的负担较小的存储器及其驱动方法。 本发明包括一个存储单元，其中存储单元包括位线和字线与插在它们之间的绝缘体交叉的区域中的存储元件，列解码器和包括时钟反相器的选择器。 时钟反相器的输入节点连接到位线，而输出节点连接到数据线。 在形成时钟反相器的串联连接的多个晶体管中，源极或漏极连接到高电位侧VDD上的电源的P型晶体管的栅极和N型晶体管的栅极 源极或漏极连接到低电位侧的电源VSS连接到列解码器。

公开(公告)号：US07166863B2

公开(公告)日：2007-01-23

申请号：US10941823

申请日：2004-09-16

申请人： Shunpei Yamazaki ,  Kiyoshi Kato ,  Atsuo Isobe ,  Hidekazu Miyairi ,  Hideomi Suzawa ,  Yutaka Shionoiri ,  Hiroyuki Miyake

发明人： Shunpei Yamazaki ,  Kiyoshi Kato ,  Atsuo Isobe ,  Hidekazu Miyairi ,  Hideomi Suzawa ,  Yutaka Shionoiri ,  Hiroyuki Miyake

IPC分类号： H01L29/04 ,  H01L31/036

CPC分类号： H01L21/02609 ,  H01L21/2026 ,  H01L27/12 ,  H01L27/1281 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78675 ,  H01L29/78696

摘要： A semiconductor element which is capable of operating at a high speed, high in an electric current drive capability, and small in fluctuation among a plurality of elements, and a semiconductor device including the semiconductor element are provided. The semiconductor element has a first crystalline semiconductor region including plural crystal orientations without practically having a grain boundary on an insulating surface, the first crystalline semiconductor region being provided to be jointly connected to a conductive region including the first crystalline semiconductor region and a second crystalline semiconductor region, in which the conductive region is provided astride insulating films extending in a linear stripe pattern.

摘要翻译： 提供能够高速运行，电流驱动能力高，多个元件之间波动小的半导体元件，以及包括半导体元件的半导体器件。 半导体元件具有包括多个晶体取向的第一晶体半导体区域，而绝缘表面实际上不具有晶界，第一晶体半导体区域被设置为共同连接到包括第一晶体半导体区域的导电区域和第二晶体半导体区域 区域，其中导电区域被设​​置成跨过线性条纹图案延伸的绝缘膜。

公开(公告)号：US20050047266A1

公开(公告)日：2005-03-03

申请号：US10890173

申请日：2004-07-14

申请人： Yutaka Shionoiri ,  Tomoaki Atsumi ,  Kiyoshi Kato

发明人： Yutaka Shionoiri ,  Tomoaki Atsumi ,  Kiyoshi Kato

IPC分类号： G11C17/18 ,  G11C7/10 ,  G11C7/12 ,  G11C8/00 ,  G11C11/4094 ,  G11C11/418 ,  G11C11/419 ,  G11C17/08 ,  G11C17/12 ,  H03K17/00 ,  H03K17/687 ,  H03K17/693

CPC分类号： G11C7/1096 ,  G11C7/1078 ,  G11C7/12 ,  G11C11/4094 ,  G11C17/12

摘要： According to the invention, mounting area is decreased and yield is improved by decreasing the number of elements, and a memory with less burden on peripheral circuitry and a driving method thereof are provided. The invention comprises a memory cell including a memory element in a region where a bit line and a word line cross with an insulator interposed between them, a column decoder, and a selector including a clocked inverter. An input node of the clocked inverter is connected to the bit line while an output node is connected to a data line. Among a plurality of transistors connected in series which form the clocked inverter, a gate of a P-type transistor of which source or drain is connected to a power source on the high potential side VDD and a gate of an N-type transistor of which source or drain is connected to a power source on the low potential side VSS are connected to the column decoder.

摘要翻译： 根据本发明，通过减少元件的数量来减小安装面积并提高产量，并且提供了对外围电路的负担较小的存储器及其驱动方法。 本发明包括一个存储单元，其中存储单元包括位线和字线与插在它们之间的绝缘体交叉的区域中的存储元件，列解码器和包括时钟反相器的选择器。 时钟反相器的输入节点连接到位线，而输出节点连接到数据线。 在形成时钟反相器的串联连接的多个晶体管中，源极或漏极连接到高电位侧VDD上的电源的P型晶体管的栅极和N型晶体管的栅极 源极或漏极连接到低电位侧的电源VSS连接到列解码器。

公开(公告)号：US20050007156A1

公开(公告)日：2005-01-13

申请号：US10899048

申请日：2004-07-27

申请人： Yutaka Shionoiri ,  Kiyoshi Kato ,  Munehiro Azami

发明人： Yutaka Shionoiri ,  Kiyoshi Kato ,  Munehiro Azami

IPC分类号： G11C7/06 ,  G11C11/413 ,  H03K5/22

CPC分类号： H03F3/45179 ,  G01R19/00 ,  G11C7/062 ,  G11C11/4091 ,  G11C11/413 ,  G11C2207/063 ,  H03F3/45183 ,  H03F3/45188 ,  H03F2203/45396 ,  H03F2203/45506 ,  H03F2203/45546 ,  H03F2203/45551 ,  H03F2203/45702 ,  H03F2203/45726

摘要： A sense amplifier according to the present invention for detecting a potential difference of signals input to a first input terminal and a second input terminal, includes a first means for applying voltages corresponding to threshold voltages of first and second transistors to gate-source voltages of the first and second transistors, and a second means for transferring signals input to the first and second input terminals to gates of the first and second transistors. In this case, a threshold variation of the first and second transistors is corrected.

摘要翻译： 根据本发明的用于检测输入到第一输入端和第二输入端的信号的电位差的读出放大器包括：第一装置，用于将对应于第一和第二晶体管的阈值电压的电压施加到栅极源电压 第一和第二晶体管，以及用于将输入到第一和第二输入端的信号传送到第一和第二晶体管的栅极的第二装置。 在这种情况下，校正第一和第二晶体管的阈值变化。

公开(公告)号：US08624548B2

公开(公告)日：2014-01-07

申请号：US13018791

申请日：2011-02-01

申请人： Shunpei Yamazaki ,  Jun Koyama ,  Yutaka Shionoiri

发明人： Shunpei Yamazaki ,  Jun Koyama ,  Yutaka Shionoiri

IPC分类号： H02J7/02 ,  H02J7/00

CPC分类号： B60L11/182 ,  B60L5/005 ,  B60L11/1829 ,  B60L11/1833 ,  B60L2200/26 ,  B60L2200/32 ,  B60L2200/34 ,  H01F38/14 ,  H02J5/005 ,  H02J7/025 ,  H02J17/00 ,  H02J50/12 ,  H02J50/20 ,  H02J50/90 ,  Y02T10/7005 ,  Y02T10/7011 ,  Y02T10/7016 ,  Y02T10/7072 ,  Y02T10/92 ,  Y02T90/12 ,  Y02T90/121 ,  Y02T90/122 ,  Y02T90/125 ,  Y02T90/14

摘要： An object is to provide a moving object structure capable of reducing power loss caused when power is supplied from a power feeding device to a moving object by wireless communication. Another object is to provide a moving object structure capable of reducing the strength of a radio wave radiated to the surroundings. Before power is supplied to a moving object, a radio wave for alignment of antennas is output from a power feeding device. That is, radio waves are output from a power feeding device in two stages. In a first stage, a radio wave is output to align positions of antennas of the power feeding device and the moving object. In a second stage, a radio wave is output to supply power from the power feeding device to the moving object.

摘要翻译： 本发明的目的是提供一种移动物体结构，能够减少通过无线通信从供电装置向移动物体供电时引起的功率损失。 另一个目的是提供能够降低辐射到周围环境的无线电波的强度的移动物体结构。 在向运动物体供电之前，从供电装置输出用于对准天线的无线电波。 也就是说，无线电波从两个阶段的馈电装置输出。 在第一阶段，输出无线电波以对准馈电装置和移动物体的天线位置。 在第二阶段，输出无线电波以从供电装置向运动物体供电。

公开(公告)号：US20110309688A1

公开(公告)日：2011-12-22

申请号：US13156483

申请日：2011-06-09

申请人： Shunpei Yamazaki ,  Jun Koyama ,  Yoshiyuki Kurokawa ,  Yutaka Shionoiri

发明人： Shunpei Yamazaki ,  Jun Koyama ,  Yoshiyuki Kurokawa ,  Yutaka Shionoiri

IPC分类号： H02J17/00

CPC分类号： H02J50/80 ,  H02J7/025 ,  H02J17/00 ,  H02J50/10 ,  H02J50/12 ,  H02J50/20 ,  H02J50/40 ,  H02J50/90 ,  Y10T307/944

摘要： An object is to provide a power feeding system and a power feeding method which are higher convenient for a power feeding user on the power receiving side. Another object is to provide a power feeding system and a power feeding method which can offer efficient services by determining or managing a power feeding user and controlling the amount of power supplied to the power receiver appropriately by a company on the power feeding side. A power feeding device which supplies power to a power receiver wirelessly manages the power receiver on the basis of identification information of the power receiver and controls power transmitted to the power receiver on the basis of position information of the power receiver.

摘要翻译： 目的在于提供对受电方的供电用户更为方便的供电系统和供电方式。 另一个目的是提供一种供电系统和馈电方法，其可以通过确定或管理供电用户并且由馈电侧的公司适当地控制供应给电力接收器的电力量来提供有效的服务。 基于电力接收器的识别信息，向电力接收器供电的供电装置，根据电力接收机的识别信息，无线地对电力接收机进行管理，根据电力接收机的位置信息，控制发送给电力接收装置的电力。

公开(公告)号：US07324097B2

公开(公告)日：2008-01-29

申请号：US10833862

申请日：2004-04-28

申请人： Jun Koyama ,  Munehiro Azami ,  Yutaka Shionoiri ,  Tomoaki Atsumi

发明人： Jun Koyama ,  Munehiro Azami ,  Yutaka Shionoiri ,  Tomoaki Atsumi

IPC分类号： G09G5/00

CPC分类号： H03K19/018578 ,  G09G3/3208 ,  G09G3/3225 ,  G09G3/3685 ,  G09G2310/0289 ,  G09G2310/0291

摘要： A level shifter that accommodates lower driving voltage of a driver circuit and has a sufficient capability of converting the amplitude of an input signal even when the voltage amplitude of the input signal is low is provided. A level shifter utilizing a current mirror circuit 150 and a differential circuit 160 is used in a portion for converting the voltage amplitude of the signal. Since the potential difference of a signal input through transistors 105 and 106 to the differential circuit 120 is amplified and outputted, the voltage amplitude can be normally converted without influence of the threshold of a transistor even when the voltage amplitude of the input signal is low.

摘要翻译： 提供了一种电平移位器，其适应驱动电路的较低驱动电压，并且即使当输入信号的电压幅度低时也具有足够的转换输入信号的幅度的能力。 在用于转换信号的电压幅度的部分中使用利用电流镜电路150和差分电路160的电平移位器。 由于通过晶体管105和106输入到差分电路120的信号的电位差被放大并输出，所以即使当输入信号的电压幅度低时，也可以不影响晶体管的阈值而正常地转换电压幅度。

公开(公告)号：US07268756B2

公开(公告)日：2007-09-11

申请号：US10650930

申请日：2003-08-29

申请人： Jun Koyama ,  Yutaka Shionoiri ,  Hiroyuki Miyake ,  Yasuhiro Hirayama ,  Buyeol Lee

发明人： Jun Koyama ,  Yutaka Shionoiri ,  Hiroyuki Miyake ,  Yasuhiro Hirayama ,  Buyeol Lee

IPC分类号： G09G3/36

CPC分类号： G09G3/3688 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2310/0297 ,  G09G2320/0233

摘要： A liquid crystal display device having analog buffer circuits, which is reduced in luminance fluctuation is provided. A source signal line driver circuit has a plurality of analog buffer circuits, the plurality of source signal lines and the plurality of analog buffer circuits constitute a circuit group, and source signal lines connected to the analog buffer circuits are switched their connections to different analog buffer circuits each time a new period is started. Therefore, output fluctuation among the analog buffer circuits is averaged and a uniform image can be displayed on the screen.

摘要翻译： 提供一种具有减少亮度波动的模拟缓冲电路的液晶显示装置。 源信号线驱动电路具有多个模拟缓冲电路，多个源极信号线和多个模拟缓冲电路构成电路组，连接到模拟缓冲电路的源极信号线将其连接切换到不同的模拟缓冲器 每次启动一个新的时期的电路。 因此，模拟缓冲电路之间的输出波动被平均化并且可以在屏幕上显示均匀的图像。

公开(公告)号：US07190297B2

公开(公告)日：2007-03-13

申请号：US11311167

申请日：2005-12-20

申请人： Jun Koyama ,  Yutaka Shionoiri

发明人： Jun Koyama ,  Yutaka Shionoiri

IPC分类号： H03M1/66

CPC分类号： G09G3/3688 ,  G09G3/20 ,  G09G2310/027 ,  G09G2310/08 ,  G09G2320/0252 ,  G11C19/00 ,  G11C19/28 ,  H03M9/00

摘要： A digital driver for display devices which can prevent the delay of digital data and the extended transition time of the digital data, and thus can make good display, and a display device including the above-mentioned digital driver are disclosed. The digital driver according to the present invention is constituted in such a manner that, by successively inputting digital data to a shift register, the digital data are shifted in the shift register, and the resulting output is sent out to latch circuits. Since the digital data are directly inputted to the shift register, the distance over which the data lines are laid around can be shortened, the increase in load due to the laying-around of the data lines which has so far been a problem can be prevented, and the delay of the digital data and the extended transition time of the digital data can be prevented.

摘要翻译： 一种用于显示装置的数字驱动器，其可以防止数字数据的延迟和数字数据的延长的转换时间，并且因此可以进行良好的显示，并且公开了包括上述数字驱动器的显示装置。 根据本发明的数字驱动器以这样的方式构成，即通过将数字数据连续地输入到移位寄存器，数字数据在移位寄存器中移位，并将所得到的输出发送到锁存电路。 由于数字数据被直接输入到移位寄存器，所以可以缩短数据线的铺设距离，因此可以防止由于到目前为止存在问题的数据线的铺设而导致的负载增加。 ，并且可以防止数字数据的延迟和数字数据的扩展转换时间。