公开(公告)号：US07741716B1

公开(公告)日：2010-06-22

申请号：US11269301

申请日：2005-11-08

申请人： Girish Venkitachalam ,  Irfan Rahim ,  Peter John McElheny

发明人： Girish Venkitachalam ,  Irfan Rahim ,  Peter John McElheny

IPC分类号： H01L23/44 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/05 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/45099

摘要： Integrated circuit bond pads are provided for forming wire bonds to integrated circuit package pins. Each pad uses a bond pad structure that provides room for under-pad circuitry. The under-pad circuitry can be connected to other circuitry on the integrated circuit, thereby providing efficient use of circuit real estate. The bond pad structures are formed in the dielectric stack portion of the integrated circuit using dummy bond pads and bond pad support structures. Bond pad support structures may be formed from metal in metal interconnect layers. Vias may be used to connect the bond pad support structures to each other and to the dummy bond pads. Bond pad support structures may be formed in a polysilicon layer at the bottom of the dielectric stack. A contact layer contains metal plugs that connect the polysilicon bond pad support structures to the lowermost metal-layer bond pad support structures.

摘要翻译： 提供集成电路接合焊盘用于形成集成电路封装引脚的引线接合。 每个焊盘使用焊盘结构，为欠焊盘电路提供空间。 底垫电路可以连接到集成电路上的其他电路，从而提供有效利用电路的不动产。 接合焊盘结构使用虚拟焊盘和焊盘支撑结构形成在集成电路的电介质叠层部分中。 焊盘支撑结构可以由金属互连层中的金属形成。 可以使用通孔将接合焊盘支撑结构彼此连接到虚拟焊盘。 焊盘支撑结构可以形成在介电叠层底部的多晶硅层中。 接触层包含将多晶硅接合焊盘支撑结构连接到最下面的金属层接合焊盘支撑结构的金属插头。

公开(公告)号：US07400480B2

公开(公告)日：2008-07-15

申请号：US11890933

申请日：2007-08-07

申请人： Cheng-Hsiung Huang ,  Guu Lin ,  Shih-Lin S. Lee ,  Chih-Ching Shih ,  Irfan Rahim ,  Stephanie T. Tran

发明人： Cheng-Hsiung Huang ,  Guu Lin ,  Shih-Lin S. Lee ,  Chih-Ching Shih ,  Irfan Rahim ,  Stephanie T. Tran

IPC分类号： H02H3/22

CPC分类号： H01L27/0266 ,  H01L27/0251

摘要： Integrated circuits are provided that have sensitive circuitry such as programmable polysilicon fuses. Electrostatic discharge (ESD) protection circuitry is provided that prevents damage or undesired programming of the sensitive circuitry in the presence of an electrostatic discharge event. The electrostatic discharge protection circuitry may have a power ESD device that limits the voltage level across the sensitive circuitry to a maximum voltage and that draws current away from the sensitive circuitry when exposed to ESD signals. The electrostatic discharge protection circuitry may also have an ESD margin circuit that helps to prevent current flow through the sensitive circuitry when the maximum voltage is applied across the sensitive circuitry.

摘要翻译： 提供具有诸如可编程多晶硅保险丝等敏感电路的集成电路。 提供静电放电（ESD）保护电路，防止在存在静电放电事件时敏感电路的损坏或不期望的编程。 静电放电保护电路可以具有电源ESD器件，其将敏感电路两端的电压电平限制到最大电压，并且当暴露于ESD信号时，其将电流从敏感电路吸取。 静电放电保护电路还可以具有ESD余量电路，当在敏感电路上施加最大电压时，该余量电路有助于防止电流流经敏感电路。

公开(公告)号：US07291546B1

公开(公告)日：2007-11-06

申请号：US10872618

申请日：2004-06-21

申请人： Irfan Rahim ,  Fangyun Richter

发明人： Irfan Rahim ,  Fangyun Richter

IPC分类号： H01L21/8247

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/66825

摘要： A method of fabricating a non-volatile memory cell on a semiconductor substrate is disclosed. An area of a first region of the semiconductor substrate designated for a layer of floating polysilicon is blocked while a second region of the semiconductor substrate designated for a layer of non-floating polysilicon is exposed. Exposed regions of the semiconductor substrate are doped with charges.

摘要翻译： 公开了一种在半导体衬底上制造非易失性存储单元的方法。 指定用于浮动多晶硅层的半导体衬底的第一区域的区域被封闭，而指定用于非浮动多晶硅层的第二半导体衬底的区域被暴露。 半导体衬底的暴露区域掺杂有电荷。

公开(公告)号：US07210115B1

公开(公告)日：2007-04-24

申请号：US10884612

申请日：2004-07-02

申请人： Irfan Rahim ,  Yow-Juang (Bill) Liu

发明人： Irfan Rahim ,  Yow-Juang (Bill) Liu

IPC分类号： G06F17/50

CPC分类号： G06F17/5054 ,  G06F17/5036

摘要： Methods and apparatus for designing and producing programmable logic devices are provided. A logic design system may be used to analyze various implementations of a desired logic design for a programmable logic device integrated circuit. The logic design system may be used to produce configuration data for the programmable logic device in accordance with an optimized implementation. A logic circuit for a programmable logic device can be analyzed by taking into account the effects of hotspots, power supply voltage drops, and signal congestion on device performance. By modeling the performance of transistors and other components using position-dependent and signal-dependent variables such as temperature, voltage, and capacitance, the effects of congestion on device performance can be characterized and an optimum implementation of the logic design in a programmable logic device can be obtained.

摘要翻译： 提供了设计和制造可编程逻辑器件的方法和设备。 可以使用逻辑设计系统来分析用于可编程逻辑器件集成电路的期望逻辑设计的各种实现。 逻辑设计系统可以用于根据优化的实现来产生可编程逻辑器件的配置数据。 可以通过考虑热点，电源电压降和信号拥塞对器件性能的影响来分析可编程逻辑器件的逻辑电路。 通过使用位置相关和信号相关变量（如温度，电压和电容）对晶体管和其他组件的性能进行建模，可以对设备性能拥塞的影响进行表征，并在可编程逻辑器件中实现逻辑设计 可以获得。

公开(公告)号：US20070069764A1

公开(公告)日：2007-03-29

申请号：US11535065

申请日：2006-09-26

申请人： David Lewis ,  Vaughn Betz ,  Irfan Rahim ,  Peter McElheny ,  Yow-Juang Liu ,  Bruce Pedersen

发明人： David Lewis ,  Vaughn Betz ,  Irfan Rahim ,  Peter McElheny ,  Yow-Juang Liu ,  Bruce Pedersen

IPC分类号： H03K19/173

CPC分类号： G06F17/5054 ,  H03K5/133 ,  H03K19/00369 ,  H03K2005/00058 ,  H03K2005/00156 ,  H03K2217/0018

摘要： A programmable logic device (PLD) includes a delay circuit and a body-bias generator. The delay circuit has a delay configured to represent a delay of user circuit implement in the PLD. The body-bias generator is configured to adjust the body bias of a transistor within the user circuit. The body-bias generator adjusts the body bias of the transistor in response to a level derived from the signal propagation delay of the delay circuit.

摘要翻译： 可编程逻辑器件（PLD）包括延迟电路和体偏置发生器。 延迟电路具有被配置为表示PLD中的用户电路实现的延迟的延迟。 体偏置发生器被配置为调整用户电路内的晶体管的体偏置。 体偏置发生器响应于从延迟电路的信号传播延迟导出的电平来调节晶体管的体偏置。

公开(公告)号：US07173320B1

公开(公告)日：2007-02-06

申请号：US10427777

申请日：2003-04-30

申请人： Irfan Rahim

发明人： Irfan Rahim

IPC分类号： H01L29/00 ,  H01L29/82 ,  H01L43/00 ,  H01L27/082

CPC分类号： H01L29/7394 ,  H01L29/0696 ,  H01L29/7317 ,  H01L29/78624

摘要： A lateral bipolar transistor includes an emitter region, a base region, a collector region, and a gate disposed over the base region. A bias line is connected to the gate for applying a bias voltage thereto during operation of the transistor. The polarity of the bias voltage is such as to create an accumulation layer in the base under the gate. The accumulation layer provides a low-resistance path for the transistor base current, thus reducing the base resistance of the transistor.

摘要翻译： 横向双极晶体管包括发射极区域，基极区域，集电极区域和设置在基极区域上的栅极。 偏置线连接到栅极，以在晶体管的工作期间施加偏置电压。 偏置电压的极性使得在栅极下方的基极中产生积聚层。 累积层为晶体管基极电流提供低电阻通路，从而降低晶体管的基极电阻。

公开(公告)号：US06933591B1

公开(公告)日：2005-08-23

申请号：US10687199

申请日：2003-10-16

申请人： Lakhbeer S. Sidhu ,  Irfan Rahim

发明人： Lakhbeer S. Sidhu ,  Irfan Rahim

IPC分类号： H01L23/525 ,  H01L23/58

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： Programmable fuses for integrated circuits are provided. The fuses may be based on polysilicon or crystalline silicon fuse links coated with silicide or other conductive thin films. Fuses may be formed on silicon-on-insulator (SOI) substrates. A fuse may be blown by applying a programming current to the fuse link. The silicon or polysilicon in the fuses may be provided with a p-n junction. When a fuse is programmed, the silicide or other conductive film forms an open circuit. This forces current though the underlying p-n junction. Unlike conventional silicided polysilicon fuses, fuses with p-n junctions change their qualitative behavior when programmed. Unprogrammed fuses behave like resistors, while programmed fuses behave like diodes. The presence of the p-n junction allows sensing circuitry to determine in a highly accurate qualitative fashion whether a given fuse has been programmed.

摘要翻译： 提供集成电路的可编程保险丝。 保险丝可以基于涂覆有硅化物或其它导电薄膜的多晶硅或晶体硅熔丝链。 可以在绝缘体上硅（SOI）衬底上形成保险丝。 通过向熔丝链路施加编程电流可能会熔断保险丝。 保险丝中的硅或多晶硅可以设置有p-n结。 当熔丝被编程时，硅化物或其它导电膜形成开路。 这通过下面的p-n结强迫电流。 与传统的硅化多晶硅保险丝不同，p-n结的保险丝在编程时会改变其定性行为。 未编程的保险丝与电阻器类似，而编程的保险丝就像二极管。 p-n结的存在允许感测电路以高度精确的定性方式确定给定的保险丝是否已被编程。

公开(公告)号：US06207991B1

公开(公告)日：2001-03-27

申请号：US09045269

申请日：1998-03-20

申请人： Irfan Rahim

发明人： Irfan Rahim

IPC分类号： H01L29792

CPC分类号： H01L27/11526 ,  H01L21/823828 ,  H01L21/823857 ,  H01L27/11529 ,  H01L27/11536 ,  H01L27/11546

摘要： A method of forming non-volatile memory (e.g., an EEPROM device) and a CMOS device (e.g., a RAM), on a single die or chip, and a structure formed by the method. In one embodiment, the control gate of the storage transistor as well as the isolation gate of the isolation transistor may be formed during the same manufacturing process step, and thus may be formed of the same gate poly material and may have similar thickness.

摘要翻译： 在单个芯片或芯片上形成非易失性存储器（例如，EEPROM器件）和CMOS器件（例如，RAM）的方法以及通过该方法形成的结构。 在一个实施例中，存储晶体管的控制栅极以及隔离晶体管的隔离栅极可以在相同的制造工艺步骤期间形成，并且因此可以由相同的栅极多晶材料形成并且可以具有类似的厚度。

公开(公告)号：US5900763A

公开(公告)日：1999-05-04

申请号：US317673

申请日：1994-10-11

申请人： Irfan Rahim ,  Bor-Yuan Hwang ,  Kuntal Joardar

发明人： Irfan Rahim ,  Bor-Yuan Hwang ,  Kuntal Joardar

IPC分类号： H01L21/761 ,  H01L27/02 ,  H01L27/088 ,  H01L21/26

CPC分类号： H01L27/088 ,  H01L21/761 ,  H01L27/0203

摘要： An integrated circuit (10) provides analog and digital circuitry on a common substrate (12). A first digital circuit (14) operates in combination with an analog circuit (18) to perform a useful function. A second duplicate digital circuit (26) is disposed adjacent to the first digital circuit and operates out-of-phase with respect to the first digital circuit. The second duplicate digital circuit introduces voltage spikes equal and opposite to the voltage spikes introduced into the substrate by the first digital circuit. The equal and opposite voltage spikes tend to cancel and thereby minimize cross-talk between the digital and analog circuits. A guard ring (16,28) surrounds each of the first and second digital circuits and the analog circuit to reduce voltage spikes into the substrates. By minimizing cross-talk, the analog circuit operates without interference from the digital circuits.

摘要翻译： 集成电路（10）在公共基板（12）上提供模拟和数字电路。 第一数字电路（14）与模拟电路（18）组合工作以执行有用的功能。 第二重复数字电路（26）被布置为与第一数字电路相邻并且相对于第一数字电路进行异相操作。 第二重复数字电路引入与由第一数字电路引入衬底的电压尖峰相等和相反的电压尖峰。 相等和相反的电压尖峰趋于抵消，从而最小化数字和模拟电路之间的串扰。 保护环（16,28）围绕第一和第二数字电路和模拟电路中的每一个以减少到基板的电压尖峰。 通过最小化串扰，模拟电路在数字电路没有干扰的情况下工作。

公开(公告)号：US08711614B1

公开(公告)日：2014-04-29

申请号：US13052374

申请日：2011-03-21

申请人： Andy L. Lee ,  Irfan Rahim ,  Lu Zhou ,  Madhuri Mailavaram ,  Srinivas Perisetty

发明人： Andy L. Lee ,  Irfan Rahim ,  Lu Zhou ,  Madhuri Mailavaram ,  Srinivas Perisetty

IPC分类号： G11C11/34

CPC分类号： G11C8/10

摘要： Memory elements are provided that exhibit immunity to soft error upset events when subjected to radiation strikes such as high-energy atomic particle strikes. The memory elements may each have four inverter-like transistor pairs that form a bistable element and a pair of address transistors. There may be four nodes in the transistor each of which is associated with a respective one of the four inverter-like transistor pairs. There may be two control transistors each of which is coupled between the transistors in a respective one of the inverter-like transistor pairs. During data writing operations, the two control transistors may be turned off to temporarily decouple the transistors in two of the four inverter-like transistor pairs.

摘要翻译： 提供了存储器元件，当受到诸如高能量原子粒子撞击的辐射攻击时，其表现出对软错误失调事件的抗扰性。 存储器元件可以各自具有形成双稳态元件和一对地址晶体管的四个反相器状晶体管对。 晶体管中可能存在四个节点，每个节点与四个逆变器状晶体管对中的相应一个相关联。 可以存在两个控制晶体管，每个控制晶体管耦合在逆变器状晶体管对的相应一个中的晶体管之间。 在数据写入操作期间，可以关闭两个控制晶体管，以暂时将四个反相器状晶体管对中的两个中的晶体管去耦。