公开(公告)号：US07749778B2

公开(公告)日：2010-07-06

申请号：US11619307

申请日：2007-01-03

申请人： Kaushik Chanda ,  Lawrence Clevenger ,  Timothy J. Dalton ,  Louis L. C. Hsu ,  Chih-Chao Yang

发明人： Kaushik Chanda ,  Lawrence Clevenger ,  Timothy J. Dalton ,  Louis L. C. Hsu ,  Chih-Chao Yang

IPC分类号： H01L21/66

CPC分类号： G01R31/2858 ,  H01L22/14 ,  H01L2924/0002 ,  Y10S438/927 ,  H01L2924/00

摘要： A method of monitoring and testing electro-migration and time dependent dielectric breakdown includes forming an addressable wiring test array, which includes a plurality or horizontally disposed metal wiring and a plurality of segmented, vertically disposed probing wiring, performing a single row continuity/resistance check to determine which row of said metal wiring is open, performing a full serpentine continuity/resistance check, and determining a position of short defects.

摘要翻译： 一种监测和测试电迁移和时间依赖介电击穿的方法包括形成可寻址布线测试阵列，其包括多个或水平布置的金属布线和多个分段垂直布置的探测布线，执行单行连续性/电阻检查 以确定所述金属布线的哪一行是打开的，执行完全蛇形连续性/电阻检查，以及确定短缺陷的位置。

公开(公告)号：US20080160656A1

公开(公告)日：2008-07-03

申请号：US11619307

申请日：2007-01-03

申请人： Kaushik Chanda ,  Lawrence Clevenger ,  Timothy J. Dalton ,  Louis L. C. Hsu ,  Chih-Chao Yang

发明人： Kaushik Chanda ,  Lawrence Clevenger ,  Timothy J. Dalton ,  Louis L. C. Hsu ,  Chih-Chao Yang

IPC分类号： H01L21/66 ,  G01R31/26

CPC分类号： G01R31/2858 ,  H01L22/14 ,  H01L2924/0002 ,  Y10S438/927 ,  H01L2924/00

摘要： A method of monitoring and testing electro-migration and time dependent dielectric breakdown includes forming an addressable wiring test array, which includes a plurality or horizontally disposed metal wiring and a plurality of segmented, vertically disposed probing wiring, performing a single row continuity/resistance check to determine which row of said metal wiring is open, performing a full serpentine continuity/resistance check, and determining a position of short defects.

摘要翻译： 一种监测和测试电迁移和时间依赖介电击穿的方法包括形成可寻址布线测试阵列，其包括多个或水平布置的金属布线和多个分段垂直布置的探测布线，执行单行连续性/电阻检查 以确定所述金属布线的哪一行是打开的，执行完全蛇形连续性/电阻检查，以及确定短缺陷的位置。

公开(公告)号：US07312529B2

公开(公告)日：2007-12-25

申请号：US11160669

申请日：2005-07-05

申请人： Lawrence Clevenger ,  Mukta G. Farooq ,  Louis L. Hsu ,  William F. Landers ,  Donna S. Zupanski-Nielsen ,  Carl J. Radens ,  Chih-Chao Yang

发明人： Lawrence Clevenger ,  Mukta G. Farooq ,  Louis L. Hsu ,  William F. Landers ,  Donna S. Zupanski-Nielsen ,  Carl J. Radens ,  Chih-Chao Yang

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L23/40

CPC分类号： H05K3/3436 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/12 ,  H01L24/17 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/06102 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/1403 ,  H01L2224/49109 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H05K2201/094 ,  H05K2201/09736 ,  H05K2201/09845 ,  Y02P70/613 ,  H01L2224/29099 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An electrical structure and method comprising a first substrate electrically and mechanically connected to a second substrate. The first substrate comprises a first electrically conductive pad and a second electrically conductive pad. The second substrate comprises a third electrically conductive pad, a fourth electrically conductive pad, and a first electrically conductive member. The fourth electrically conductive pad comprises a height that is different than a height of the first electrically conductive member. The electrically conductive member is electrically and mechanically connected to the fourth electrically conductive pad. A first solder ball connects the first electrically conductive pad to the third electrically conductive pad. The first solder ball comprises a first diameter. A second solder ball connects the second electrically conductive pad to the first electrically conductive member. The second solder ball comprises a second diameter. The first diameter is greater than said second diameter.

摘要翻译： 一种电结构和方法，包括电和机械地连接到第二衬底的第一衬底。 第一基板包括第一导电焊盘和第二导电焊盘。 第二基板包括第三导电焊盘，第四导电焊盘和第一导电部件。 第四导电焊盘包括与第一导电构件的高度不同的高度。 导电构件电连接和机械地连接到第四导电垫。 第一焊球将第一导电焊盘连接到第三导电焊盘。 第一焊球包括第一直径。 第二焊球将第二导电焊盘连接到第一导电构件。 第二焊球包括第二直径。 第一直径大于所述第二直径。

公开(公告)号：US20060281338A1

公开(公告)日：2006-12-14

申请号：US11160213

申请日：2005-06-14

申请人： Kaushik Chanda ,  Hazara Rathore ,  Paul McLaughlin ,  Robert Edwards ,  Lawrence Clevenger ,  Andrew Cowley ,  Chih-Chao Yang ,  Conrad Barile

发明人： Kaushik Chanda ,  Hazara Rathore ,  Paul McLaughlin ,  Robert Edwards ,  Lawrence Clevenger ,  Andrew Cowley ,  Chih-Chao Yang ,  Conrad Barile

IPC分类号： H01L21/00

CPC分类号： H01L22/14 ,  G01R31/2642 ,  G01R31/2831

摘要： The invention predicts premature dielectric breakdown in a semiconductor. At least one dielectric breakdown mode is calculated for the semiconductor wafer. If a one mode is calculated, premature dielectric breakdown will be associated with any semiconductor with a breakdown voltage less than a predetermined standard deviation of a plurality of breakdown voltages within said calculated mode. If multiple modes are calculated, the mode that most accurately represents dielectric breakdown for the semiconductor wafer is determined and premature dielectric breakdown will be associated with any semiconductor with a breakdown voltage less than a predetermined standard of the calculated mode that most accurately represents dielectric breakdown for the semiconductor wafer.

摘要翻译： 本发明预测半导体中的过早的介质击穿。 对于半导体晶片计算至少一个绝缘击穿模式。 如果计算一种模式，则过早的介电击穿将与在所述计算模式中具有小于多个击穿电压的预定标准偏差的击穿电压的任何半导体相关联。 如果计算多个模式，则确定最准确地代表半导体晶片的电介质击穿的模式，并且过早的电介质击穿将与任何具有小于计算模式的预定标准的击穿电压的半导体相关联，其最准确地表示用于 半导体晶片。

公开(公告)号：US20070115018A1

公开(公告)日：2007-05-24

申请号：US11163948

申请日：2005-11-04

申请人： Kaushik Chanda ,  Birendra Agarwala ,  Lawrence Clevenger ,  Andrew Cowley ,  Ronald Filippi ,  Jason Gill ,  Tom Lee ,  Baozhen Li ,  Paul McLaughlin ,  Du Nguyen ,  Hazara Rathore ,  Timothy Sullivan ,  Chih-Chao Yang

发明人： Kaushik Chanda ,  Birendra Agarwala ,  Lawrence Clevenger ,  Andrew Cowley ,  Ronald Filippi ,  Jason Gill ,  Tom Lee ,  Baozhen Li ,  Paul McLaughlin ,  Du Nguyen ,  Hazara Rathore ,  Timothy Sullivan ,  Chih-Chao Yang

IPC分类号： G01R31/26

CPC分类号： G01R31/2858 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A microelectronic element such as a chip or microelectronic wiring substrate is provided which includes a plurality of conductive interconnects for improved resistance to thermal stress. At least some of the conductive interconnects include a metallic plate, a metallic connecting line and an upper metallic via. The metallic connecting line has an upper surface at least substantially level with an upper surface of the metallic plate, an inner end connected to the metallic plate at one of the peripheral edges, and an outer end horizontally displaced from the one peripheral edge. The metallic connecting line has a width much smaller than the width of the one peripheral edge of the metallic plate and has length greater than the width of the one peripheral edge. The upper metallic via has a bottom end in contact with the metallic connecting line at a location that is horizontally displaced from the one peripheral edge by at least about 3 microns (μm).

摘要翻译： 提供了诸如芯片或微电子布线基板的微电子元件，其包括用于改善耐热应力的多个导电互连。 至少一些导电互连件包括金属板，金属连接线和上金属通孔。 所述金属连接线具有与所述金属板的上表面至少基本平齐的上表面，在所述周边边缘中的一个处连接到所述金属板的内端和从所述一个周边边缘水平移位的外端。 金属连接线的宽度远小于金属板的一个周边边缘的宽度，并且其长度大于一个周边边缘的宽度。 上金属通孔在与一个外围边缘水平位移至少约3微米（mum）的位置处具有与金属连接线接触的底端。

公开(公告)号：US20080107149A1

公开(公告)日：2008-05-08

申请号：US12004011

申请日：2007-12-19

申请人： Kaushik Chanda ,  Birendra Agarwala ,  Lawrence Clevenger ,  Andrew Cowley ,  Ronald Filippi ,  Jason Gill ,  Tom Lee ,  Baozhen Li ,  Paul McLaughlin ,  Du Nguyen ,  Hazara Rathore ,  Timothy Sullivan ,  Chih-Chao Yang

发明人： Kaushik Chanda ,  Birendra Agarwala ,  Lawrence Clevenger ,  Andrew Cowley ,  Ronald Filippi ,  Jason Gill ,  Tom Lee ,  Baozhen Li ,  Paul McLaughlin ,  Du Nguyen ,  Hazara Rathore ,  Timothy Sullivan ,  Chih-Chao Yang

IPC分类号： G01N25/72 ,  G01R31/26

CPC分类号： G01R31/2858 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A microelectronic element such as a chip or microelectronic wiring substrate is provided which includes a plurality of conductive interconnects for improved resistance to thermal stress. At least some of the conductive interconnects include a metallic plate, a metallic connecting line and an upper metallic via. The metallic connecting line has an upper surface at least substantially level with an upper surface of the metallic plate, an inner end connected to the metallic plate at one of the peripheral edges, and an outer end horizontally displaced from the one peripheral edge. The metallic connecting line has a width much smaller than the width of the one peripheral edge of the metallic plate and has length greater than the width of the one peripheral edge. The upper metallic via has a bottom end in contact with the metallic connecting line at a location that is horizontally displaced from the one peripheral edge by at least about 3 microns (μm).

摘要翻译： 提供了诸如芯片或微电子布线基板的微电子元件，其包括用于改善耐热应力的多个导电互连。 至少一些导电互连件包括金属板，金属连接线和上金属通孔。 所述金属连接线具有与所述金属板的上表面至少基本平齐的上表面，在所述周边边缘中的一个处连接到所述金属板的内端和从所述一个周边边缘水平移位的外端。 金属连接线的宽度远小于金属板的一个周边边缘的宽度，并且其长度大于一个周边边缘的宽度。 上金属通孔在与一个外围边缘水平位移至少约3微米（mum）的位置处具有与金属连接线接触的底端。

公开(公告)号：US20060231945A1

公开(公告)日：2006-10-19

申请号：US10907873

申请日：2005-04-19

申请人： Anil Chinthakindi ,  Lawrence Clevenger ,  Tom Lee ,  Gerald Matusiewicz ,  Conal Murray ,  Chih-Chao Yang

发明人： Anil Chinthakindi ,  Lawrence Clevenger ,  Tom Lee ,  Gerald Matusiewicz ,  Conal Murray ,  Chih-Chao Yang

IPC分类号： H01L23/34

CPC分类号： H01L23/5228 ,  H01L23/3677 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure and method are disclosed for heat dissipation relative to a heat generating element in a semiconductor device. The structure includes a plurality of heat transmitting lines partially vertically coincidental with the heat generating element, and at least one interconnecting path from each heat transmitting line to a substrate of the semiconductor device. In one embodiment, the heat generating element includes a resistor in a non-first metal level. The invention is compatible with conventional BEOL interconnect schemes, minimizes the amount of heat transfer from the resistor to the surrounding interconnect wiring, thus eliminating the loss of current carrying capability in the wiring.

摘要翻译： 公开了相对于半导体器件中的发热元件的散热的结构和方法。 该结构包括多个与发热元件垂直一致的传热线，以及从每个传热线到半导体器件的基板的至少一个互连路径。 在一个实施例中，发热元件包括非第一金属水平的电阻器。 本发明与传统的BEOL互连方案兼容，使得从电阻器到周围互连布线的传热量最小化，从而消除了布线中的载流能力的损失。

公开(公告)号：US20060108651A1

公开(公告)日：2006-05-25

申请号：US10904660

申请日：2004-11-22

申请人： Huilong Zhu ,  Lawrence Clevenger ,  Omer Dokumaci ,  Oleg Gluschenkov ,  Kaushik Kumar ,  Carl Radens ,  Dureseti Chidambarrao

发明人： Huilong Zhu ,  Lawrence Clevenger ,  Omer Dokumaci ,  Oleg Gluschenkov ,  Kaushik Kumar ,  Carl Radens ,  Dureseti Chidambarrao

IPC分类号： H01L29/94

CPC分类号： H01L21/26506 ,  H01L21/26586 ,  H01L29/0843 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

摘要： A novel transistor structure and method for fabrication the same. The novel transistor structure comprises first and second source/drain (S/D) regions whose top surfaces are lower than a top surface of the channel region of the transistor structure. The method for fabricating the transistor structure starts out with a planar semiconductor layer and a gate stack on top of the semiconductor layer. Then, top regions of the semiconductor layer on opposing sides of the gate stack are removed. Then, regions beneath the removed regions are doped to form lowered S/D regions of the transistor structure

摘要翻译： 一种新颖的晶体管结构及其制造方法。 新颖的晶体管结构包括顶表面低于晶体管结构的沟道区的顶表面的第一和第二源极/漏极（S / D）区域。 用于制造晶体管结构的方法从在半导体层顶部的平面半导体层和栅叠层开始。 然后，去除栅极堆叠的相对侧上的半导体层的顶部区域。 然后，去除区域下方的区域被掺杂以形成晶体管结构的降低的S / D区域

公开(公告)号：US20070092990A1

公开(公告)日：2007-04-26

申请号：US11163523

申请日：2005-10-21

申请人： Michael Belyansky ,  Dureseti Chidambarrao ,  Lawrence Clevenger ,  Kaushik Kumar ,  Carl Radens

发明人： Michael Belyansky ,  Dureseti Chidambarrao ,  Lawrence Clevenger ,  Kaushik Kumar ,  Carl Radens

IPC分类号： H01L21/00 ,  H01L29/76

CPC分类号： H01L21/76804 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to an field effect transistor (FET) comprising an inverted source/drain metallic contact that has a lower portion located in a first, lower dielectric layer and an upper portion located in a second, upper dielectric layer. The lower portion of the inverted source/drain metallic contact has a larger cross-sectional area than the upper portion. Preferably, the lower portion of the inverted source/drain metallic contact has a cross-sectional area ranging from about 0.03 μm2 to about 3.15 μm2, and such an inverted source/drain metallic contact is spaced apart from a gate electrode of the FET by a distance ranging from about 0.001 μm to about 5 μm.

摘要翻译： 本发明涉及一种场效应晶体管（FET），其包括反向的源极/漏极金属接触，其具有位于第一下部电介质层中的下部和位于第二上部电介质层中的上部。 倒置的源极/漏极金属触点的下部具有比上部更大的横截面面积。 优选地，倒置的源极/漏极金属接触件的下部具有约0.03毫米2至约3.15微米的横截面积，并且这样的反相源 /漏极金属触点与FET的栅电极间隔约0.001μm至约5μm的距离。

公开(公告)号：US20080042174A1

公开(公告)日：2008-02-21

申请号：US11923075

申请日：2007-10-24

申请人： Michael Belyansky ,  Dureseti Chidambarrao ,  Lawrence Clevenger ,  Kaushik Kumar ,  Carl Radens

发明人： Michael Belyansky ,  Dureseti Chidambarrao ,  Lawrence Clevenger ,  Kaushik Kumar ,  Carl Radens

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/76804 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to an field effect transistor (FET) comprising an inverted source/drain metallic contact that has a lower portion located in a first, lower dielectric layer and an upper portion located in a second, upper dielectric layer. The lower portion of the inverted source/drain metallic contact has a larger cross-sectional area than the upper portion. Preferably, the lower portion of the inverted source/drain metallic contact has a cross-sectional area ranging from about 0.03 μm2 to about 3.15 μm2, and such an inverted source/drain metallic contact is spaced apart from a gate electrode of the FET by a distance ranging from about 0.001 μm to about 5 μm.

摘要翻译： 本发明涉及一种场效应晶体管（FET），其包括反向的源极/漏极金属接触，其具有位于第一下部电介质层中的下部和位于第二上部电介质层中的上部。 倒置的源极/漏极金属触点的下部具有比上部更大的横截面面积。 优选地，倒置的源极/漏极金属接触件的下部具有约0.03毫米2至约3.15微米的横截面积，并且这样的反相源 /漏极金属触点与FET的栅电极间隔约0.001μm至约5μm的距离。