公开(公告)号：US10984864B2

公开(公告)日：2021-04-20

申请号：US16517846

申请日：2019-07-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luca De Santis ,  Tommaso Vali ,  Kenneth J. Eldredge ,  Vishal Sarin

IPC: G11C15/04 ,  G11C16/10 ,  G11C16/04 ,  H01L27/00 ,  G11C13/06 ,  G11C29/52

Abstract: Methods include receiving a pattern to be searched in a memory having a plurality of sets of memory elements with each set coupled to a separate data line and corresponding to a same set of bit positions of the pattern. Methods further include receiving a pattern of data to be programmed into a memory, programming a first data state into one memory cell of each cell pair of a plurality of cell pairs of a memory array, and programing a second data state into another memory cell of each cell pair of the plurality of cell pairs for each bit position of the pattern. Memory configured to facilitate such methods include a plurality of cell pairs, each cell pair of the plurality of cell pairs programmed to store a same bit of data corresponding to a particular bit position of a pattern to be searched in the memory.

公开(公告)号：US20200211648A1

公开(公告)日：2020-07-02

申请号：US16235066

申请日：2018-12-28

Applicant: Micron Technology, Inc.

Inventor： Umberto Minucci ,  Tommaso Vali ,  Fernanda Irrera ,  Luca De Santis

IPC: G11C16/04 ,  G06N3/063 ,  G06F3/06

Abstract: A method can include applying a first voltage to a first memory cell to activate the first memory cell, applying a second voltage to a second memory cell coupled in series with the first memory cell to activate the second memory cell so that current flows through the first and second memory cells, and generating an output responsive to the current. The first voltage and a threshold voltage of the second memory cell can be such that the current is proportional to a product of the first voltage and the threshold voltage of the second memory cell.

公开(公告)号：US10395740B2

公开(公告)日：2019-08-27

申请号：US16003357

申请日：2018-06-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luca De Santis ,  Tommaso Vali ,  Kenneth J. Eldredge ,  Frankie F. Roohparvar

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  G11C16/26

Abstract: Memories including a data line, a plurality of strings of series-connected memory cells selectively connected to the data line, a plurality of first access lines each coupled to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells, and a plurality of second access lines each coupled to a control gate of a respective memory cell of a respective string of series-connected memory cells of the plurality of strings of series-connected memory cells, as well as methods of operating similar memories.

公开(公告)号：US10359944B2

公开(公告)日：2019-07-23

申请号：US15690320

申请日：2017-08-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luca De Santis ,  Luigi Pilolli

IPC: G11C8/00 ,  G06F3/06 ,  G11C11/4074 ,  G11C16/10 ,  G11C7/16 ,  G11C11/4096 ,  G11C7/10 ,  G06F13/16 ,  G11C16/06 ,  G06F12/0875 ,  G06F12/0893

Abstract: Apparatus including a memory array further include an analog voltage generation circuit, an analog controller, a data cache, a data cache controller, and a master controller. The master controller is configured to generate an indication in response to an interpreted command. The analog controller is configured to determine, in response to the indication, what analog voltages should be generated by the analog voltage generation circuit for the apparatus to perform the interpreted command. The data cache controller is configured to determine, in response to the indication, whether the data cache should be configured to accept data from the memory array or to provide data to the memory array for the apparatus to perform the interpreted command.

公开(公告)号：US20190050162A1

公开(公告)日：2019-02-14

申请号：US16166231

申请日：2018-10-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Frankie F. Roohparvar ,  Luca De Santis ,  Tommaso Vali ,  Kenneth J. Eldredge

IPC: G06F3/06 ,  G11C11/00 ,  G11C15/04 ,  G06F11/22 ,  G11C16/04 ,  G06F11/10

CPC classification number: G06F3/0634 ,  G06F3/0626 ,  G06F3/0632 ,  G06F3/0679 ,  G06F3/0688 ,  G06F11/1064 ,  G06F11/2263 ,  G11C11/005 ,  G11C15/046 ,  G11C16/0483

Abstract: Memory devices, and methods of operating similar memory devices, include an array of memory cells comprising a plurality of access lines each configured for biasing control gates of a respective plurality of memory cells of the array of memory cells, wherein the respective plurality of memory cells for one access line of the plurality of access lines is mutually exclusive from the respective plurality of memory cells for each remaining access line of the plurality of access lines, and a controller having a plurality of selectively-enabled operating modes and configured to selectively operate the memory device using two or more concurrently enabled operating modes of the plurality of selectively-enabled operating modes for access of the array of memory cells, with each of the enabled operating modes of the two of more concurrently enabled operating modes utilizing an assigned respective portion of the array of memory cells.

公开(公告)号：US20190018733A1

公开(公告)日：2019-01-17

申请号：US16105305

申请日：2018-08-20

Applicant: Micron Technology, Inc.

Inventor： Violante Moschiano ,  Walter Di Francesco ,  Luca De Santis ,  Giovanni Santin

IPC: G06F11/10 ,  G11C29/52 ,  H03M13/29

Abstract: A memory device includes a memory array that includes a buffer data. The memory device also includes a memory controller. The memory controller includes an error correction code (ECC) component. The memory controller further receives a status command and an indication related to the quality of the data to analyze with the ECC component. Based on a status value, the memory controller utilizes one of a plurality of error correction techniques via the ECC component to correct an error (e.g., soft state, calibration, etc.).

公开(公告)号：US20180365293A1

公开(公告)日：2018-12-20

申请号：US16113055

申请日：2018-08-27

Applicant: Micron Technology, Inc.

Inventor： Luca De Santis ,  Giulio G. Marotta ,  Marco-Domenico Tiburzi ,  Tommaso Vali ,  Frankie F. Roohparvar ,  Agostino Macerola

IPC: G06F17/30 ,  G11C16/04 ,  G11C29/50 ,  G06F12/0802 ,  G06F3/06 ,  G06F7/20 ,  G11C7/10 ,  G11C16/06 ,  G11C15/04

CPC classification number: G06F16/24558 ,  G06F3/0628 ,  G06F7/20 ,  G06F12/0802 ,  G06F2212/1021 ,  G06F2212/608 ,  G11C7/1006 ,  G11C15/046 ,  G11C16/0483 ,  G11C16/06 ,  G11C29/50004 ,  G11C29/50016

Abstract: Memory devices for facilitating pattern matching and having an array of memory cells, a plurality of key registers to store a representation of a key word, and a plurality of multiplexers, each multiplexer of the plurality of multiplexers to select a representation of a bit from a key register of the plurality of key registers to compare to data stored in the array of memory cells.

公开(公告)号：US20180210653A1

公开(公告)日：2018-07-26

申请号：US15532886

申请日：2017-01-23

Applicant: Micron Technology, Inc.

Inventor： Sivagnanam Parthasarathy ,  Terry M. Grunzke ,  Lucia Botticchio ,  Walter Di Francesco ,  Vamshi K. Indavarapu ,  Gianfranco Valeri ,  Renato C. Padilla ,  Ali Mohammadzadeh ,  Jung Sheng Hoei ,  Luca De Santis

IPC: G06F3/06 ,  G06F12/1009

CPC classification number: G06F3/064 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/1009 ,  G06F2212/1021 ,  G06F2212/2022 ,  G06F2212/7201

Abstract: The present disclosure relates to partially written block treatment. An example method comprises maintaining, internal to a memory device, a status of a last written page corresponding to a partially written block. Responsive to receiving, from a controller, a read request to a page of the partially written block, the example method can include determining, from page map information maintained internal to the memory device and from the status of the last written page, which of a number of different read trim sets to use to read the page of the partially written block corresponding to the read request.

公开(公告)号：US20180108415A1

公开(公告)日：2018-04-19

申请号：US15841490

申请日：2017-12-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luca De Santis ,  Tommaso Vali ,  Kenneth J. Eldredge ,  Vishal Sarin

IPC: G11C15/04 ,  G11C16/04 ,  G11C16/10

CPC classification number: G11C15/046 ,  G11C16/0483 ,  G11C16/10 ,  G11C29/52

Abstract: Methods include receiving a pattern to be searched in a memory having a plurality of sets of memory elements with each set coupled to a separate data line and corresponding to a same set of bit positions of the pattern. Methods further include receiving a pattern of data to be programmed into a memory, programming a first data state into one memory cell of each cell pair of a plurality of cell pairs of a memory array, and programing a second data state into another memory cell of each cell pair of the plurality of cell pairs for each bit position of the pattern. Memory configured to facilitate such methods include a plurality of cell pairs, each cell pair of the plurality of cell pairs programmed to store a same bit of data corresponding to a particular bit position of a pattern to be searched in the memory.

公开(公告)号：US20170309341A1

公开(公告)日：2017-10-26

申请号：US15645009

申请日：2017-07-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kenneth J. Eldredge ,  Frankie F. Roohparvar ,  Luca De Santis ,  Tommaso Vali

IPC: G11C16/28 ,  G11C15/00 ,  G11C15/04 ,  G11C16/04

CPC classification number: G11C16/28 ,  G11C15/00 ,  G11C15/046 ,  G11C16/0483

Abstract: Methods of operating a memory device include comparing input data to data stored in memory cells coupled to a data line, comparing a representation of a level of current in the data line to a reference, and determining that the input data potentially matches the data stored in the memory cells when the representation of the level of current in the data line is less than the reference. Methods of operating a memory device further include comparing input data to first data and to second data stored in memory cells coupled to a first data line or to a second data line, respectively, comparing representations of the levels of current in the first data line and in the second data line to a first reference and to a different second reference, and deeming one to be a closer match to the input data in response to results of the comparisons.