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    Memory cells, integrated devices, and methods of forming memory cells
    52.
    发明授权
    Memory cells, integrated devices, and methods of forming memory cells 有权
    存储单元，集成器件和形成存储单元的方法

    公开(公告)号：US09299930B2

    公开(公告)日：2016-03-29

    申请号：US14225111

    申请日：2014-03-25

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Redaelli ,  Ugo Russo ,  Agostino Pirovano ,  Simone Lavizzari

    IPC: H01L45/00

    CPC classification number: H01L45/06 ,  G11C13/0004 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/128 ,  H01L45/1286 ,  H01L45/141 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1608 ,  H01L45/165 ,  H01L45/1675

    Abstract: Some embodiments include integrated devices, such as memory cells. The devices may include chalcogenide material, an electrically conductive material over the chalcogenide material, and a thermal sink between the electrically conductive material and the chalcogenide material. The thermal sink may be of a composition that includes an element in common with the electrically conductive material and includes an element in common with the chalcogenide material. Some embodiments include a method of forming a memory cell. Chalcogenide material may be formed over heater material. Electrically conductive material may be formed over the chalcogenide material. A thermal sink may be formed between the electrically conductive material and the chalcogenide material. The thermal sink may be of a composition that includes an element in common with the electrically conductive material and includes an element in common with the chalcogenide material.

    Abstract translation: 一些实施例包括集成设备，诸如存储器单元。 这些装置可以包括硫族化物材料，在硫族化物材料上的导电材料，以及在导电材料和硫族化物材料之间的散热器。 散热器可以是包括与导电材料相同的元件的组合物，并且包括与硫族化物材料相同的元件。 一些实施例包括形成存储器单元的方法。 可以在加热器材料上形成硫族化物材料。 可以在硫族化物材料上形成导电材料。 可以在导电材料和硫族化物材料之间形成散热器。 散热器可以是包括与导电材料相同的元件的组合物，并且包括与硫族化物材料相同的元件。

    Assemblies Comprising Memory Cells and Select Gates; and Methods of Forming Assemblies
    53.
    发明申请
    Assemblies Comprising Memory Cells and Select Gates; and Methods of Forming Assemblies 有权

    公开(公告)号：US20250149072A1

    公开(公告)日：2025-05-08

    申请号：US19013290

    申请日：2025-01-08

    Applicant: Micron Technology, Inc.

    Inventor： Ugo Russo

    IPC: G11C7/10 ,  G11C8/12 ,  G11C11/56 ,  G11C16/08 ,  G11C19/32 ,  H10B41/35 ,  H10B43/27

    Abstract: Some embodiments include an assembly having a stack of alternating dielectric levels and conductive levels. Channel material pillars extend through the stack. Some of the channel material pillars are associated with a first sub-block, and others of the channel material pillars are associated with a second sub-block. Memory cells are along the channel material pillars. An insulative level is over the stack. A select gate configuration is over the insulative level. The select gate configuration includes a first conductive gate structure associated with the first sub-block, and includes a second conductive gate structure associated with the second sub-block. The first and second conductive gate structures are laterally spaced from one another by an intervening insulative region. The first and second conductive gate structures have vertically-spaced conductive regions, and have vertically-extending conductive structures which electrically couple the vertically-spaced conductive regions to one another. Some embodiments include methods of forming assemblies.

    Transient and stable state read operations of a memory device
    54.
    发明授权
    Transient and stable state read operations of a memory device 有权

    公开(公告)号：US12224016B2

    公开(公告)日：2025-02-11

    申请号：US17888781

    申请日：2022-08-16

    Applicant: Micron Technology, Inc.

    Inventor： Ugo Russo ,  Karan Banerjee ,  Shyam Sunder Raghunathan

    IPC: G11C16/26

    Abstract: A memory system may implement a read operation including a delay if a channel is at stable state, and may implement a read operation without a delay if the channel is in a transient state. Upon receiving a read command to a set of memory cells sharing the channel, the memory system may determine whether the channel is in a stable or transient state. If the channel is in a stable state, the memory system may perform a read operation including a delay between boosting the channel and driving respective word lines, such that the channel partially discharges prior to driving the word lines. If the channel is in a transient state, the memory system may perform a read operation without a delay between boosting the channel and driving the word lines.

    SELECTIVELY PROGRAMMING RETIRED WORDLINES OF A MEMORY DEVICE
    57.
    发明公开
    SELECTIVELY PROGRAMMING RETIRED WORDLINES OF A MEMORY DEVICE 审中-公开

    公开(公告)号：US20230214133A1

    公开(公告)日：2023-07-06

    申请号：US18090449

    申请日：2022-12-28

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Kishore Kumar Muchherla ,  Akira Goda ,  Jeffrey S. McNeil ,  Niccolo' Righetti ,  Silvia Beltrami ,  Violante Moschiano ,  Ugo Russo

    IPC: G06F3/06

    CPC classification number: G06F3/0619 ,  G06F3/0679 ,  G06F3/0659

    Abstract: A memory device comprises an array of memory cells organized into a plurality of wordlines, and a processing device to perform processing operations that receive a program command specifying a memory unit and data comprising first received data, where the plurality of wordlines includes one or more first active data wordlines and a group of consecutive retired wordlines. The processing operations also program the specified data to the memory unit by programming the first received data to the one or more first active data wordlines, identifying a first retired boundary wordline that is in the group of consecutive retired wordlines and is adjacent to one of the first active data wordlines, generating a first data pattern comprising a first plurality of threshold voltage levels, and programming the first data pattern to the first retired boundary wordline.

    Adjustable NAND write performance
    60.
    发明授权
    Adjustable NAND write performance 有权

    公开(公告)号：US11526277B2

    公开(公告)日：2022-12-13

    申请号：US17157410

    申请日：2021-01-25

    Applicant: Micron Technology, Inc.

    Inventor： Giuseppe Cariello ,  Mauro Luigi Sali ,  Stefano Falduti ,  Ugo Russo

    IPC: G06F3/06

    Abstract: Devices and techniques for adjustable memory device write performance are described herein. An accelerated write request can be received at a memory device from a controller of the memory device. The memory device can identify that a target block for external writes is opened as a multi-level cell block. The memory device can then write data for the accelerated write request to the target block using a single-level cell encoding.

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