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    3D semiconductor device and structure
    52.
    发明授权
    3D semiconductor device and structure 有权

    公开(公告)号：US10950581B2

    公开(公告)日：2021-03-16

    申请号：US17065424

    申请日：2020-10-07

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach ,  Brian Cronquist

    IPC: H01L25/065 ,  H01L23/00 ,  H01L21/66 ,  H01L25/00

    Abstract: A 3D semiconductor device including: a first level including a first layer, the first layer including first transistors, and where the first level includes a second layer, the second layer including first interconnections; a second level overlaying the first level, where the second level includes a third layer, the third layer including second transistors, where the second level includes a fourth layer, the fourth layer including second interconnections; and a plurality of connection paths, where the plurality of connection paths provides connections from a plurality of the first transistors to a plurality of the second transistors, where the second level is bonded to the first level, where the bonded includes oxide to oxide bond regions, where the bonded includes metal to metal bond regions, where the second level includes at least one memory array, where the third layer includes crystalline silicon, where the second layer includes radio frequency type circuits.

    3D semiconductor device and structure
    53.
    发明授权
    3D semiconductor device and structure 有权

    公开(公告)号：US10651054B2

    公开(公告)日：2020-05-12

    申请号：US16115519

    申请日：2018-08-28

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak Sekar

    IPC: H01L21/48 ,  H01L23/498 ,  H01L27/092 ,  H01L23/34 ,  H01L27/02 ,  H01L21/8234 ,  H01L27/06 ,  H01L25/065 ,  H01L23/60 ,  H01L23/522 ,  H01L23/367 ,  H01L25/00 ,  H01L27/098 ,  H01L23/373 ,  H01L23/50 ,  H01L21/8238

    Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors and a first metal layer, where the first metal layer includes interconnecting the first transistors forming, at least in part a plurality of logic gates; a plurality of second transistors overlaying, at least in part the first single crystal layer; a plurality of third transistors overlaying, at least in part the second transistors; a second metal layer overlaying, at least in part the third transistors; Input/Output pads to provide connection to external devices, a local power grid to distribute power to the logic gates, where the third transistors are aligned to the first transistors with less than 40 nm misalignment, where the first single crystal layer includes a Phase Lock Loop (“PLL”) structure connected to at least one of the Input/Output pads, where a memory cell includes at least one of the third transistors.

    3D semiconductor device and structure
    57.
    发明授权
    3D semiconductor device and structure 有权

    公开(公告)号：US10157909B2

    公开(公告)日：2018-12-18

    申请号：US15862616

    申请日：2018-01-04

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

    IPC: H01L27/06 ,  H01L29/78

    Abstract: A 3D semiconductor device, the device including: a first layer including first transistors each including a silicon channel; a second layer including second transistors each including a silicon channel, the second layer overlaying the first transistors, where at least one of the second transistors is at least partially self-aligned to at least one of the first transistors; and a third layer including third transistors each including a single crystal silicon channel, the third layer underlying the first transistors, where a plurality of the third transistors form a logic circuit, and where the logic circuit is aligned to the second transistors with less than 200 nm alignment error, where the first layer thickness is less than one micron, and where the first transistor is a junction-less transistor.

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