公开(公告)号：US20110234162A1

公开(公告)日：2011-09-29

申请号：US13131917

申请日：2009-12-15

申请人： Takuya Kinoshita ,  Yoshio Shimoida

发明人： Takuya Kinoshita ,  Yoshio Shimoida

IPC分类号： H02J7/04

CPC分类号： H01M10/441 ,  H01M10/482 ,  H02J7/0016

摘要： A secondary battery system that is light in weight and low in cost is provided, which comprises a plurality of secondary batteries connected in series. A plurality of first diodes each has an anode connected to a negative electrode of the corresponding secondary battery. A plurality of second diodes each has a cathode connected to a positive electrode of the corresponding secondary battery. A plurality of capacitors is each connected to a junction portion between the cathode of the first diode and the anode of the second diode. An alternating current power source is commonly connected to the junction portions through the capacitors.

摘要翻译： 提供重量轻且成本低的二次电池系统，其包括串联连接的多个二次电池。 多个第一二极管各自具有连接到相应的二次电池的负极的阳极。 多个第二二极管各自具有连接到相应的二次电池的正极的阴极。 多个电容器各自连接到第一二极管的阴极和第二二极管的阳极之间的接合部分。 交流电源通常通过电容器连接到接合部分。

公开(公告)号：US07768035B2

公开(公告)日：2010-08-03

申请号：US12066145

申请日：2006-08-02

申请人： Yoshio Shimoida ,  Tetsuya Hayashi ,  Masakatsu Hoshi ,  Hideaki Tanaka ,  Shigeharu Yamagami

发明人： Yoshio Shimoida ,  Tetsuya Hayashi ,  Masakatsu Hoshi ,  Hideaki Tanaka ,  Shigeharu Yamagami

IPC分类号： H01L31/0328

CPC分类号： H01L29/0847 ,  H01L21/0445 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/267 ,  H01L29/66068 ,  H01L29/7828

摘要： A semiconductor device has a semiconductor base of a first conductivity type; a hetero semiconductor region in contact with the semiconductor base; a gate electrode adjacent to a portion of a junction between the hetero semiconductor region and the semiconductor base across a gate insulating film; a source electrode connected to the hetero semiconductor region; and a drain electrode connected to the semiconductor base. The hetero semiconductor region has a band gap different from that of the semiconductor base. The hetero semiconductor region includes a first hetero semiconductor region and a second hetero semiconductor region. The first hetero semiconductor region is formed before the gate insulating film is formed. The second hetero semiconductor region is formed after the gate insulating film is formed.

摘要翻译： 半导体器件具有第一导电类型的半导体基底; 与半导体基底接触的异质半导体区域; 与栅极绝缘膜相邻的异质半导体区域和半导体基底之间的结的部分相邻的栅电极; 连接到所述异质半导体区的源电极; 以及连接到半导体基底的漏电极。 异质半导体区域具有与半导体基底不同的带隙。 异质半导体区域包括第一异质半导体区域和第二异质半导体区域。 在形成栅极绝缘膜之前形成第一异质半导体区域。 在形成栅极绝缘膜之后形成第二异质半导体区域。

公开(公告)号：US07749845B2

公开(公告)日：2010-07-06

申请号：US11988944

申请日：2006-06-26

申请人： Shigeharu Yamagami ,  Masakatsu Hoshi ,  Tetsuya Hayashi ,  Hideaki Tanaka ,  Yoshio Shimoida

发明人： Shigeharu Yamagami ,  Masakatsu Hoshi ,  Tetsuya Hayashi ,  Hideaki Tanaka ,  Yoshio Shimoida

IPC分类号： H01L21/336

CPC分类号： H01L29/1608 ,  H01L29/267 ,  H01L29/66068 ,  H01L29/7827

摘要： A method of manufacturing a semiconductor device having a polycrystalline silicon layer (5) includes; a step of forming a mask layer (7) on the polycrystalline silicon layer (5); a step of forming a side wall (8) that is provided on a side face of the mask layer (7) and covers part of the polycrystalline silicon layer (6); a step of doping an impurity (52) into the polycrystalline silicon layer (5) by using at least one of the mask layer (7) and the side wall (8) as a mask; and a step of etching the polycrystalline silicon layer (5, 6) by using at least one of the mask layer (7) and the side wall (8) as a mask.

摘要翻译： 一种制造具有多晶硅层（5）的半导体器件的方法包括： 在多晶硅层（5）上形成掩模层（7）的步骤; 形成设置在掩模层（7）的侧面并覆盖多晶硅层（6）的一部分的侧壁（8）的步骤; 通过使用掩模层（7）和侧壁（8）中的至少一个作为掩模将杂质（52）掺杂到多晶硅层（5）中的步骤; 以及通过使用掩模层（7）和侧壁（8）中的至少一个作为掩模来蚀刻多晶硅层（5,6）的步骤。

公开(公告)号：US07521731B2

公开(公告)日：2009-04-21

申请号：US11444433

申请日：2006-06-01

申请人： Yoshio Shimoida ,  Masakatsu Hoshi ,  Tetsuya Hayashi ,  Hideaki Tanaka

发明人： Yoshio Shimoida ,  Masakatsu Hoshi ,  Tetsuya Hayashi ,  Hideaki Tanaka

IPC分类号： H01L31/0328

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/66068 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/8083

摘要： A semiconductor device of the invention includes a first conductive type semiconductor base substrate; and a switching mechanism which is formed on a first main surface of the semiconductor base substrate and switches ON/OFF of a current. In the semiconductor base substrate, a plurality of columnar hetero-semiconductor regions are formed at spaced intervals within the semiconductor substrate, and the hetero-semiconductor regions are made of a semiconductor material having a different band gap from the semiconductor substrate and extend between the first main surface and a second main surface opposite to the first main surface.

摘要翻译： 本发明的半导体器件包括：第一导电型半导体基底; 以及切换机构，其形成在所述半导体基板的第一主面上并切换电流的开/关。 在半导体基板中，多个柱状异质半导体区域在半导体衬底内隔开间隔地形成，并且异质半导体区域由与半导体衬底具有不同带隙的半导体材料制成，并且在第一 主表面和与第一主表面相对的第二主表面。

公开(公告)号：US07436004B2

公开(公告)日：2008-10-14

申请号：US11289460

申请日：2005-11-30

申请人： Yoshio Shimoida ,  Masakatsu Hoshi ,  Hideaki Tanaka ,  Tetsuya Hayashi ,  Toshiro Shinohara ,  Shigeharu Yamagami

发明人： Yoshio Shimoida ,  Masakatsu Hoshi ,  Hideaki Tanaka ,  Tetsuya Hayashi ,  Toshiro Shinohara ,  Shigeharu Yamagami

IPC分类号： H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109 ,  H01L31/111

CPC分类号： H01L29/7398 ,  H01L29/0834 ,  H01L29/1608 ,  H01L29/267 ,  H01L29/7391 ,  H01L29/7392 ,  H01L29/7395 ,  H01L29/7397

摘要： An aspect of the present invention provides a semiconductor device that includes, a first semiconductor body of a first conductivity type, a first switching mechanism provided on the first semiconductor body, configured and arranged to switch on/off current flowing through the semiconductor device, and a first reverse-blocking heterojunction diode provided on the semiconductor body, configured and arranged to block current reverse to the current switched on/off by the first switching mechanism.

摘要翻译： 本发明的一个方面提供一种半导体器件，其包括：第一导电类型的第一半导体本体，设置在第一半导体本体上的第一开关机构，被配置和布置成用于接通流过半导体器件的导通/截止电流;以及 设置在所述半导体本体上的第一反向阻挡异质结二极管，被配置和布置成阻止与所述第一开关机构相反的电流接通/断开。

公开(公告)号：US20070298586A1

公开(公告)日：2007-12-27

申请号：US11454818

申请日：2006-06-21

申请人： Hideaki Tanaka ,  Masakatsu Hoshi ,  Yoshio Shimoida ,  Tetsuya Hayashi

发明人： Hideaki Tanaka ,  Masakatsu Hoshi ,  Yoshio Shimoida ,  Tetsuya Hayashi

IPC分类号： H01L21/30 ,  H01L21/46

CPC分类号： H01L29/66068 ,  H01L21/6835 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/1608 ,  H01L29/267 ,  H01L29/6606 ,  H01L29/7828 ,  H01L29/861 ,  H01L2221/68363

摘要： The present invention provides a method of manufacturing a semiconductor device. The semiconductor device comprises a semiconductor base made of a first semiconductor material; and a hetero-semiconductor region made of a second semiconductor material having a different band gap from the first semiconductor material and forming a heterojunction with the semiconductor base. The formation of the heterojunction is accomplished by bonding together the semiconductor base and a substrate made of the second semiconductor material.

摘要翻译： 本发明提供一种制造半导体器件的方法。 半导体器件包括由第一半导体材料制成的半导体基底; 以及由与第一半导体材料具有不同带隙并与半导体基底形成异质结的第二半导体材料制成的异质半导体区域。 异质结的形成通过将半导体基底和由第二半导体材料制成的基底结合在一起来实现。

公开(公告)号：US20060223274A1

公开(公告)日：2006-10-05

申请号：US11377909

申请日：2006-03-16

申请人： Yoshio Shimoida ,  Masakatsu Hoshi ,  Tetsuya Hayashi ,  Hideaki Tanaka ,  Shigeharu Yamagami

发明人： Yoshio Shimoida ,  Masakatsu Hoshi ,  Tetsuya Hayashi ,  Hideaki Tanaka ,  Shigeharu Yamagami

IPC分类号： H01L21/331 ,  H01L21/8222

CPC分类号： H01L29/78 ,  H01L21/047 ,  H01L29/1608 ,  H01L29/267 ,  H01L29/66068 ,  H01L29/772 ,  H01L29/7828

摘要： In general, this disclosure describes a semiconductor device that exhibits an increased resistance and reduced leakage current in a reverse-biased state, and a method for manufacturing such a semiconductor device. For example, in one embodiment, the increased resistance in the reverse-biased state is obtained by introducing either a P+ or P− type impurity in a polycrystalline silicon layer formed on an N− type epitaxial layer. Additionally, the semiconductor device maintains a low resistance in a forward-biased state. To keep the forward-biased resistance low, the polycrystalline silicon layer in the vicinity of a gate electrode may be of an N+ type. Furthermore, an N+ type source extracting region is formed on the surface of the polycrystalline silicon layer to connect a source electrode to a drain electrode and maintain a low resistance when forward-biased.

公开(公告)号：US07042086B2

公开(公告)日：2006-05-09

申请号：US10678208

申请日：2003-10-06

申请人： Yoshio Shimoida ,  Toshiro Shinohara ,  Tetsuya Hayashi ,  Masanori Yamagiwa

发明人： Yoshio Shimoida ,  Toshiro Shinohara ,  Tetsuya Hayashi ,  Masanori Yamagiwa

IPC分类号： H01L23/34

CPC分类号： H01L25/071 ,  H01L2224/04026 ,  H01L2224/06181 ,  H01L2224/32245 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00

摘要： A stacked semiconductor module encompasses (a) a upper switching element having a first semiconductor chip, a first top electrode disposed at a top surface of the first semiconductor chip, a first bottom electrode disposed at a bottom surface of the first semiconductor chip, and a first control electrode configured to control conduction between the first top and first bottom electrodes; (b) a first wiring plate disposed beneath the upper switching element, electrically connected to the first bottom electrode; and (c) a lower switching element disposed beneath the wiring plate, having a second semiconductor chip, a second top electrode disposed at a top surface of the second semiconductor chip, electrically connected to the first wiring plate, a second bottom electrode disposed at a bottom surface of the second semiconductor chip, and a second control electrode configured to control conduction between the second top and second bottom electrodes.

摘要翻译： 叠层半导体模块包括（a）具有第一半导体芯片的上开关元件，设置在第一半导体芯片的顶表面的第一顶电极，设置在第一半导体芯片的底表面处的第一底电极，以及 第一控制电极，被配置为控制第一顶部电极和第一底部电极之间的导通; （b）设置在所述上​​开关元件下方的电连接到所述第一底电极的第一布线板; 以及（c）设置在所述布线板下方的下开关元件，具有第二半导体芯片，设置在所述第二半导体芯片的顶表面处的第二上电极，电连接到所述第一布线板， 第二半导体芯片的底面以及第二控制电极，被配置为控制第二顶电极和第二底电极之间的导通。

公开(公告)号：US09601780B2

公开(公告)日：2017-03-21

申请号：US14119290

申请日：2012-05-22

申请人： Yusuke Kato ,  Masahiro Kojima ,  Ryutaro Mukai ,  Masato Kusakabe ,  Hiroyuki Ogino ,  Takashi Kikuchi ,  Takashi Ito ,  Satoshi Oku ,  Akiko Waki ,  Shiho Inoue ,  Yuji Muroya ,  Norihisa Waki ,  Yasuyuki Tanaka ,  Shigeo Ibuka ,  Yoshio Shimoida

发明人： Yusuke Kato ,  Masahiro Kojima ,  Ryutaro Mukai ,  Masato Kusakabe ,  Hiroyuki Ogino ,  Takashi Kikuchi ,  Takashi Ito ,  Satoshi Oku ,  Akiko Waki ,  Shiho Inoue ,  Yuji Muroya ,  Norihisa Waki ,  Yasuyuki Tanaka ,  Shigeo Ibuka ,  Yoshio Shimoida

IPC分类号： H01M4/66 ,  H01M10/0525 ,  C08K3/04 ,  C08J7/04 ,  B32B27/08 ,  B32B27/20 ,  B32B27/28 ,  B32B27/32 ,  H01M4/02

CPC分类号： H01M4/668 ,  B32B27/08 ,  B32B27/20 ,  B32B27/281 ,  B32B27/325 ,  B32B2264/10 ,  B32B2264/105 ,  B32B2307/202 ,  B32B2307/206 ,  B32B2457/10 ,  C08G2261/3324 ,  C08G2261/418 ,  C08J7/047 ,  C08J2379/08 ,  C08J2465/00 ,  C08K3/04 ,  C08K2201/001 ,  H01M4/661 ,  H01M4/663 ,  H01M4/666 ,  H01M4/667 ,  H01M10/0525 ,  H01M2004/029 ,  Y02E60/122 ,  C08L65/00

摘要： A multilayer conductive film includes a layer 1 including a conductive material containing a polymer material 1 having an alicyclic structure and conductive particles 1 and a layer 2 including a material having durability against positive electrode potential. The multilayer conductive film has stability in an equilibrium potential environment in a negative electrode and stability in an equilibrium potential environment in a positive electrode, has low electric resistance per unit area in the thickness direction, and has excellent barrier properties for a solvent of an electrolytic solution. A battery including a current collector employing the multilayer conductive film can achieve both weight reduction and durability.

公开(公告)号：US08945755B2

公开(公告)日：2015-02-03

申请号：US12121923

申请日：2008-05-16

申请人： Yasuhiro Yanagihara ,  Hideaki Horie ,  Yoshio Shimoida ,  Kyouichi Watanabe ,  Osamu Shimamura ,  Yuichiro Yamamura

发明人： Yasuhiro Yanagihara ,  Hideaki Horie ,  Yoshio Shimoida ,  Kyouichi Watanabe ,  Osamu Shimamura ,  Yuichiro Yamamura

IPC分类号： H01M4/46 ,  H01M10/0585 ,  H01M2/26 ,  H01M10/04 ,  H01M10/0525

CPC分类号： H01M10/0585 ,  H01M2/266 ,  H01M10/0413 ,  H01M10/0463 ,  H01M10/0525 ,  Y02E60/122 ,  Y02T10/7011

摘要： The disclosure discusses a secondary battery with superior durability and a vehicle configured to mount the same. The secondary battery comprises an electrode structure wherein a cathode is formed at one side of a base material layer having electrical insulating property and an anode is formed at another side of the base material layer. A plurality of electrode structures are stacked with an electrolyte layer interposed therebetween such that the cathode and anode of adjacent electrode structures are on opposite sides of the electrolyte layer.

摘要翻译： 本公开内容讨论了具有优异耐用性的二次电池和被配置为安装它的车辆。 二次电池包括电极结构，其中阴极形成在具有电绝缘性的基材层的一侧，阳极形成在基材层的另一侧。 多个电极结构层叠有电解质层，使得相邻电极结构的阴极和阳极位于电解质层的相对侧。