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    Electrically erasable and programmable non-volatile memory system with write-verify controller using two reference levels
    51.
    发明授权
    Electrically erasable and programmable non-volatile memory system with write-verify controller using two reference levels 失效
    具有写入验证控制器的电可擦除和可编程非易失性存储器系统，使用两个参考电平

    公开(公告)号：US5469444A

    公开(公告)日：1995-11-21

    申请号：US341955

    申请日：1994-11-16

    申请人： Tetsuo Endoh ,  Riichiro Shirota ,  Kazunori Ohuchi ,  Ryouhei Kirisawa ,  Seiichi Aritome ,  Tomoharu Tanaka ,  Yoshiyuki Tanaka

    发明人： Tetsuo Endoh ,  Riichiro Shirota ,  Kazunori Ohuchi ,  Ryouhei Kirisawa ,  Seiichi Aritome ,  Tomoharu Tanaka ,  Yoshiyuki Tanaka

    IPC分类号： G11C11/56 ,  G11C16/34 ,  G11C29/50 ,  G01R31/28

    CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/3404 ,  G11C16/3413 ,  G11C16/3418 ,  G11C16/3431 ,  G11C16/3459 ,  G11C29/50 ,  G06F2201/81 ,  G11C16/04 ,  G11C2029/0403 ,  G11C2211/5621

    摘要： An EEPROM includes an array of memory cell transistors, which is divided into cell blocks each including NAND cell units of series-connected cell transistors. A sense amplifier is connected to bit lines and a comparator. A data-latch circuit is connected to the comparator, for latching a write-data supplied from a data input buffer. After desired cell transistors selected for programming in a selected block are once programmed, a write-verify operation is performed. The comparator compares the actual data read from one of the programmed cell transistors with the write-data, to verify its written state. The write-verify process checks the resulting threshold voltage for variations using first and second reference voltages defining the lower-limit and upper-limit of an allowable variation range. If the comparison results under employment of the first voltage shows that an irregularly written cell transistor remains with an insufficient threshold voltage which is so low as to fail to fall within the range, the write operation continues for the same cell transistor. If the comparison results under employment of the second voltage shows that an excess-written cell transistor remains, the block is rendered "protected" at least partially.

    摘要翻译： EEPROM包括存储单元晶体管的阵列，其被分成每个包括串联连接的单元晶体管的NAND单元单元的单元块。 读出放大器连接到位线和比较器。 数据锁存电路连接到比较器，用于锁存从数据输入缓冲器提供的写入数据。 在所选择的块中选择用于编程的所需单元晶体管被一次编程之后，执行写验证操作。 比较器将从编程单元晶体管之一读取的实际数据与写入数据进行比较，以验证其写入状态。 写验证过程使用限定允许变化范围的下限和上限的第一和第二参考电压来检查所得到的阈值电压的变化。 如果使用第一电压的比较结果表明，不规则写入的单元晶体管保持不足阈值电压，其不足以落在该范围内，对于相同的单元晶体管，写操作继续进行。 如果在使用第二电压的情况下的比较结果表明剩余写入过多的单元晶体管，则该块至少部分地被“保护”。

    Electrically erasable programmable read-only memory with electric field decreasing controller
    52.
    发明授权
    Electrically erasable programmable read-only memory with electric field decreasing controller 失效
    电可擦除可编程只读存储器，具有电场降低控制器

    公开(公告)号：US5293337A

    公开(公告)日：1994-03-08

    申请号：US683733

    申请日：1991-04-11

    申请人： Seiichi Aritome ,  Riichiro Shirota ,  Ryouhei Kirisawa ,  Yoshihisa Iwata ,  Masaki Momodomi

    发明人： Seiichi Aritome ,  Riichiro Shirota ,  Ryouhei Kirisawa ,  Yoshihisa Iwata ,  Masaki Momodomi

    IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/16 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

    CPC分类号： G11C16/16 ,  G11C16/0433 ,  G11C16/0483

    摘要： A NAND cell type EEPROM has bit lines, each of which is associated with a NAND cell unit including a series array of four memory cell transistors. Each transistor is a MOSFET with a control gate and a floating gate for data storage. The memory cell transistors are connected at their control gates to word lines, respectively. One end of the NAND cell unit is connected through a first select transistor to a corresponding bit line; the other end thereof is connected via a second select transistor to a source voltage. The memory cell transistors and the select transistors are arranged in a well region formed in a substrate. In an erase mode, the bit line voltage, the substrate voltage and the well voltage are held at a high voltage, whereas the word lines are at zero volts. The gate potential of the select transistors is held at the high voltage, whereby the internal electric field of these select transistors is weakened to improve the dielectric breakdown characteristic thereof.

    摘要翻译： NAND单元型EEPROM具有位线，其各自与包括四个存储单元晶体管的串联阵列的NAND单元单元相关联。 每个晶体管是具有控制栅极和用于数据存储的浮动栅极的MOSFET。 存储单元晶体管分别在其控制栅极处连接到字线。 NAND单元单元的一端通过第一选择晶体管连接到相应的位线; 其另一端经由第二选择晶体管连接到源极电压。 存储单元晶体管和选择晶体管布置在形成在衬底中的阱区中。 在擦除模式中，位线电压，衬底电压和阱电压保持在高电压，而字线为零伏。 选择晶体管的栅极电位被保持在高电压，由此这些选择晶体管的内部电场被削弱以改善其绝缘击穿特性。

    Electrically erasable programmable read-only memory with NAND cellstructure
    53.
    发明授权
    Electrically erasable programmable read-only memory with NAND cellstructure 失效
    具有NAND单元结构的电可擦除可编程只读存储器

    公开(公告)号：US5050125A

    公开(公告)日：1991-09-17

    申请号：US272404

    申请日：1988-11-17

    申请人： Masaki Momodomi ,  Koichi Toita ,  Yasuo Itoh ,  Yoshihisa Iwata ,  Fujio Masuoka ,  Masahiko Chiba ,  Tetsuo Endo ,  Riichiro Shirota ,  Ryouhei Kirisawa

    发明人： Masaki Momodomi ,  Koichi Toita ,  Yasuo Itoh ,  Yoshihisa Iwata ,  Fujio Masuoka ,  Masahiko Chiba ,  Tetsuo Endo ,  Riichiro Shirota ,  Ryouhei Kirisawa

    IPC分类号： G11C16/04 ,  G11C16/08 ,  G11C16/30 ,  H01L27/115

    CPC分类号： H01L27/115 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/30

    摘要： An erasable programmable read-only memory with a NAND cell structure including NAND cell blocks, each of which has a selection transistor connected to the corresponding bit line and memory cell transistors connected is series. Word lines are connected to control gates of the cell transistors. In a data write mode, a selection transistor of a certain cell block containing a selected cell is rendered conductive to connect the cell block to the corresponding bit line. A control circuit is provided for applying an "L" Level voltage (approximately O V) to a word line connected to the selected cell, applying an "H" level voltage (approximately 20 V) to a word line or word lines positioned between the selected word line and a contact node connecting the cell block and a specific bit line associated therewith, applying a voltage corresponding to data to be written to the specific bit line, and applying an intermediate voltage between the "H" and "L" level voltages to non-selected bit lines, thereby writing the data in the selected cell by tunneling. If the data is logic "0" data, the intermediate voltage is applied also to the specific bit line.

    摘要翻译： 具有包括NAND单元块的NAND单元结构的可擦除可编程只读存储器，每个NAND单元块具有连接到相应位线的选择晶体管和连接的存储单元晶体管。 字线连接到单元晶体管的控制栅极。 在数据写入模式中，包含所选择的单元的某个单元块的选择晶体管被导通以将单元块连接到对应的位线。 提供控制电路，用于向连接到所选择的单元的字线施加“L”电平电压（大约为0V），对位于所选择的单元之间的字线或字线施加“H”电平电压（大约20V） 字线和连接单元块和与其相关联的特定位线的接触节点，施加与要写入特定位线的数据相对应的电压，以及将“H”和“L”电平电压之间的中间电压施加到 未选择的位线，从而通过隧道将数据写入所选择的单元。 如果数据是逻辑“0”数据，则中间电压也被施加到特定位线。

    Semiconductor device with fuse portion
    54.
    发明授权
    Semiconductor device with fuse portion 失效
    带保险丝部分的半导体器件

    公开(公告)号：US08169049B2

    公开(公告)日：2012-05-01

    申请号：US12493614

    申请日：2009-06-29

    申请人： Ryouhei Kirisawa

    发明人： Ryouhei Kirisawa

    IPC分类号： H01L23/52

    CPC分类号： H01L23/5256 ,  H01L23/3121 ,  H01L23/62 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L27/11526 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49174 ,  H01L2224/49175 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

    摘要： A semiconductor device includes: a plurality of NAND memory dies each including: a first wiring layer formed in the NAND memory die; a second wiring layer formed in the NAND memory die; a first insulation layer formed between the first wiring layer and the second wiring layer; and a first interlayer connector formed in the first insulation layer, a controller configured to control the NAND memory dies; a package housing the NAND memory dies and the controller; a connecting portion electrically connecting an inner side of the package and an outer side of the package; a first connecting wire; and a second connecting wire, wherein a resistance value per unit length of the first interlayer connector is larger than a resistance value per unit length of the first wiring layer, and wherein the first interlayer connector is cut off when a first current flows through the first interlayer connector.

    摘要翻译： 一种半导体器件包括：多个NAND存储器管芯，每个NAND存储器管芯包括：形成在NAND存储器管芯中的第一布线层; 形成在NAND存储模具中的第二布线层; 形成在所述第一布线层和所述第二布线层之间的第一绝缘层; 以及形成在所述第一绝缘层中的第一层间连接器，被配置为控制所述NAND存储器管芯的控制器; 一个容纳NAND存储器管芯和控制器的封装; 连接部，其电连接所述封装的内侧和所述封装的外侧; 第一连接线; 以及第二连接线，其中所述第一层间连接器的每单位长度的电阻值大于所述第一布线层的每单位长度的电阻值，并且其中当所述第一电流流过所述第一层间连接器时，所述第一层间连接器被切断， 层间连接器。

    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
    55.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 失效
    非易失性半导体存储器件及其制造方法

    公开(公告)号：US20100301405A1

    公开(公告)日：2010-12-02

    申请号：US12727644

    申请日：2010-03-19

    申请人： Shigeto OOTA ,  Yoshimasa Mikajiri ,  Ryouhei Kirisawa

    发明人： Shigeto OOTA ,  Yoshimasa Mikajiri ,  Ryouhei Kirisawa

    IPC分类号： H01L29/788 ,  H01L21/336

    CPC分类号： H01L29/792 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/1203 ,  H01L29/66833 ,  H01L29/7926

    摘要： A nonvolatile semiconductor memory device including first laminated bodies each having a plurality of first gate electrodes of first memory cells, second laminated bodies each having a plurality of second gate electrodes of second memory cells, gate insulating film portions located on side surfaces of the first and second laminated bodies, first semiconductor layers that are each located between the first and second laminated bodies, first select transistors connected to an uppermost one of the first memory cells, second select transistors connected to an uppermost one of the second memory cells, isolation insulating films to separate the first and second select transistors into portions on the first and second laminated body sides, and a substrate potential applying electrode located to penetrate the isolation insulating films from a front surface side to a back surface side and connected to the first semiconductor layers.

    摘要翻译： 一种非易失性半导体存储器件，包括：第一层叠体，其具有第一存储单元的多个第一栅电极;第二层叠体，每个第二层叠体具有第二存储单元的多个第二栅电极，位于第一存储单元的侧表面的栅绝缘膜部; 第二层叠体，各自位于第一和第二层叠体之间的第一半导体层，连接到第一存储单元中的最上面的第一选择晶体管，连接到第二存储单元中最上面的第一选择晶体管，隔离绝缘膜 将第一和第二选择晶体管分离成第一和第二层叠体侧的部分，以及位于从前表面侧到背面侧穿透隔离绝缘膜并连接到第一半导体层的衬底电位施加电极。

    Electrically erasable programmable read-only memory with electric field decreasing controller
    57.
    发明授权
    Electrically erasable programmable read-only memory with electric field decreasing controller 失效
    电可擦除可编程只读存储器，具有电场降低控制器

    公开(公告)号：US5402373A

    公开(公告)日：1995-03-28

    申请号：US201036

    申请日：1994-02-24

    申请人： Seiichi Aritome ,  Riichiro Shirota ,  Ryouhei Kirisawa ,  Yoshihisa Iwata ,  Masaki Momodomi

    发明人： Seiichi Aritome ,  Riichiro Shirota ,  Ryouhei Kirisawa ,  Yoshihisa Iwata ,  Masaki Momodomi

    IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/16 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

    CPC分类号： G11C16/16 ,  G11C16/0433 ,  G11C16/0483

    摘要： A NAND cell type EEPROM has bit lines, each of which is associated with a NAND cell unit including a series array of four memory cell transistors. Each transistor is a MOSFET with a control gate and a floating gate for data storage. The memory cell transistors are connected at their control gates to word lines, respectively. One end of the NAND cell unit is connected through a first select transistor to a corresponding bit line; the other end thereof is connected via a second select transistor to a source voltage. The memory cell transistors and the select transistors are arranged in a well region formed in a substrate. In an erase mode, the bit line voltage, the substrate voltage and the well voltage are held at a high voltage, whereas the word lines are at zero volts. The gate potential of the select transistors is held at the high voltage, whereby the internal electric field of these select transistors is weakened to improve the dielectric breakdown characteristic thereof.

    摘要翻译： NAND单元型EEPROM具有位线，其各自与包括四个存储单元晶体管的串联阵列的NAND单元单元相关联。 每个晶体管是具有控制栅极和用于数据存储的浮动栅极的MOSFET。 存储单元晶体管分别在其控制栅极处连接到字线。 NAND单元单元的一端通过第一选择晶体管连接到相应的位线; 其另一端经由第二选择晶体管连接到源极电压。 存储单元晶体管和选择晶体管布置在形成在衬底中的阱区中。 在擦除模式中，位线电压，衬底电压和阱电压保持在高电压，而字线为零伏。 选择晶体管的栅极电位被保持在高电压，由此这些选择晶体管的内部电场被削弱以改善其绝缘击穿特性。

    Non-volatile semiconductor memory device with nand type memory cell arrays
    59.
    发明授权
    Non-volatile semiconductor memory device with nand type memory cell arrays 失效
    具有n型存储单元阵列的非易失性半导体存储器件

    公开(公告)号：US5978265A

    公开(公告)日：1999-11-02

    申请号：US746176

    申请日：1991-08-15

    申请人： Ryouhei Kirisawa ,  Riichiro Shirota ,  Ryozo Nakayama ,  Seiichi Aritome ,  Masaki Momodomi ,  Yasuo Itoh ,  Fujio Masuoka

    发明人： Ryouhei Kirisawa ,  Riichiro Shirota ,  Ryozo Nakayama ,  Seiichi Aritome ,  Masaki Momodomi ,  Yasuo Itoh ,  Fujio Masuoka

    IPC分类号： G11C17/12 ,  G11C16/04 ,  G11C16/10 ,  G11C17/00 ,  G11C11/34

    CPC分类号： G11C16/0483 ,  G11C16/10

    摘要： An electrically erasable programmable read-only memory is disclosed which has programmable memory cells connected to parallel bit lines provided above a semiconductor substrate. The memory cells include NAND cell blocks each of which has a series array of memory cell transistors. Parallel word lines are connected to the control gates of the memory cell transistors, respectively. In a data write mode, a selection transistor in a certain NAND cell block including a selected memory cell is rendered conductive to connect the certain cell block to a corresponding bit line associated therewith. Under such a condition, electrons are tunnel-injected into a floating gate of the selected memory cell transistor, and the threshold value of the certain transistor is increased to be a positive value. A logical data is thus written in the selected memory cell transistor. The data in the selected cell transistor is erased by discharging carriers accumulated in the floating gate thereof to its drain or the substrate, so that the threshold value of the certain transistor is decreased to be a negative value.

    摘要翻译： 公开了一种电可擦除可编程只读存储器，其具有连接到设置在半导体衬底上的并行位线的可编程存储器单元。 存储单元包括NAND单元块，每个NAND单元具有存储单元晶体管的串联阵列。 并行字线分别连接到存储单元晶体管的控制栅极。 在数据写入模式中，包括所选择的存储单元的某个NAND单元块中的选择晶体管被导通以将特定单元块连接到与其相关联的相应位线。 在这种条件下，电子被隧道注入到所选择的存储单元晶体管的浮动栅极中，并且特定晶体管的阈值增加到正值。 因此，逻辑数据被写入所选择的存储单元晶体管中。 通过将其浮置栅极中累积的载流子放电到其漏极或衬底来擦除所选择的单元晶体管中的数据，使得某个晶体管的阈值降低为负值。