公开(公告)号：US12079082B2

公开(公告)日：2024-09-03

申请号：US17801992

申请日：2021-03-02

Applicant: Micron Technology, Inc.

Inventor： Christophe Laurent ,  Riccardo Muzzetto

IPC: G06F11/00 ,  G06F11/10

CPC classification number: G06F11/1076

Abstract: The present disclosure relates to a method comprising the steps of defining a minimum number of parity cells for storing parity data, the minimum number of parity cells corresponding to a minimum Error Correction Code (ECC) correction capability, defining a maximum number of parity cells for storing the parity data, the maximum number of parity cells corresponding to a maximum ECC correction capability, storing payload content in a plurality of memory cells of a memory array, and, based on a current status of the memory cells storing the payload, selecting a number of parity cells to be used for storing the parity data between the minimum number and the maximum number. The payload is stored in at least part of the parity cells which are not selected to store parity data. Related memory devices and systems are also herein disclosed.

公开(公告)号：US20240241789A1

公开(公告)日：2024-07-18

申请号：US18404043

申请日：2024-01-04

Applicant: Micron Technology, Inc.

Inventor： Christophe Vincent Antoine Laurent ,  Riccardo Muzzetto

IPC: G06F11/10 ,  G06F11/07

CPC classification number: G06F11/1068 ,  G06F11/076 ,  G06F11/1012

Abstract: In some aspects, the techniques described herein relate to a method including: selecting a plurality of coding tables, the plurality of coding tables including an encoding table and a decoding table; building an error table using the plurality of coding tables, the error table representing potential bit errors that may occur during reading and writing to a memory device using the plurality of coding tables; masking the error table to eliminate error values in the error table meeting a preconfigured condition; determining if the error table includes one or more errors in invalid positions; and storing the error table when the error table does not include one or more errors in invalid positions.

公开(公告)号：US12039176B2

公开(公告)日：2024-07-16

申请号：US17952614

申请日：2022-09-26

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Christophe Vincent Antoine Laurent ,  Riccardo Muzzetto

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0629 ,  G06F3/0679

Abstract: The present disclosure relates to providing multiple error correction code protection levels in memory. One device includes an array of memory cells and an operating circuit for managing operation of the array. The operating circuit comprises an encoding unit configured to generate a codeword for a first error correction code (ECC) protection level and a second ECC protection level, and decoding unit configured to perform an ECC operation on the codeword at the first ECC protection level and the second ECC protection level. The codeword comprises payload data stored in a plurality of memory cells of the array, and parity data associated with the payload data stored in parity cells of the array.

公开(公告)号：US20240221856A1

公开(公告)日：2024-07-04

申请号：US17802009

申请日：2021-03-02

Applicant: Micron Technology, Inc.

Inventor： Christophe Laurent ,  Riccardo Muzzetto

IPC: G11C29/42 ,  G11C29/52

CPC classification number: G11C29/42 ,  G11C29/52

Abstract: The present disclosure relates to a memory device comprising an array of memory cells and an operating circuit for managing the operation of the array, the operating circuit comprising an encoding unit configured to generate a codeword, the codeword comprising payload data stored in a plurality of memory cells of the array, parity data associated with the payload data stored in parity cells of the memory array, wherein a number of parity cells to be used to store the parity data is selectable based on a status of the plurality of memory cells and is related to a selected Error Correction Code (ECC) protection level, and extra payload data stored in unused parity cells, the device further comprising a decoding unit configured to perform an ECC operation on the stored codeword based on the selected ECC protection level. The encoding unit and the decoding unit comprise respective circuit portions configured to be selectively activable based on the selected ECC protection level, and each circuit portion is configured to manage a respective predetermined payload and parity quantity of the codeword.

公开(公告)号：US20240194284A1

公开(公告)日：2024-06-13

申请号：US17801467

申请日：2021-03-02

Applicant: Micron Technology, Inc.

Inventor： Christophe Laurent ,  Riccardo Muzzetto

IPC: G11C29/42 ,  G11C29/12 ,  G11C29/52

CPC classification number: G11C29/42 ,  G11C29/1201 ,  G11C29/52

Abstract: The present disclosure relates to a method for operating an array of memory cells, the method comprising the steps of storing user data in a plurality of memory cells of the memory array, storing parity data associated with the user data in parity cells of the memory array, wherein a number of used parity cells is selected based on a status of the memory cells and is related to a selected Error Correction Code (ECC) correction capability, and performing an ECC operation on the plurality of memory cells, the ECC correction capability being based on the selected number of used parity cells. Related memory devices and systems are also herein disclosed.

公开(公告)号：US20240062824A1

公开(公告)日：2024-02-22

申请号：US17890912

申请日：2022-08-18

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Riccardo Muzzetto

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/26

CPC classification number: G11C16/102 ,  G11C16/08 ,  G11C16/26

Abstract: The present disclosure includes apparatuses, methods, and systems for balancing data in memory. An embodiment includes a memory having a group of memory cells, wherein each respective memory cell is programmable to one of three possible data states, and circuitry to balance data programmed to the group between the three possible data states by determining whether the data programmed to the group is balanced for any one of the three possible data states, and upon determining the data programmed to the group is not balanced for any one of the three possible data states apply a rotational mapping algorithm to the data programmed to the group until the data is balanced for any one of the three possible data states and apply a Knuth algorithm to the data of the group programmed to the two of the three possible data states that were not balanced by the rotational mapping algorithm.

公开(公告)号：US20240053902A1

公开(公告)日：2024-02-15

申请号：US17887239

申请日：2022-08-12

Applicant: Micron Technology, Inc.

Inventor： Christophe Vincent Antoine Laurent ,  Riccardo Muzzetto

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0629 ,  G06F3/0673

Abstract: Methods, systems, and devices for balanced codewords for reducing a selected state in memory cells are described. A memory device may divide a sequence of data bits into sets of bits associated with different bit-positions in a coding scheme. The memory device may then balance a first codeword that includes the first set of the data bits in the binary domain to reach a target ratio of logic values for the codeword. Using the first codeword and the other set(s) of data bits, the memory device may balance the remaining two states in the state domain to reach an overall target distribution of the three states. The memory device may then generate one or more codeword(s) for the other set(s) of data bits so that the memory device can write all of the codewords to ternary cells.

公开(公告)号：US11880571B2

公开(公告)日：2024-01-23

申请号：US17044150

申请日：2020-05-13

Applicant: Micron Technology, Inc.

Inventor： Riccardo Muzzetto ,  Ferdinando Bedeschi ,  Umberto di Vincenzo

IPC: G06F3/06

CPC classification number: G06F3/0614 ,  G06F3/0629 ,  G06F3/0653 ,  G06F3/0679

Abstract: The present disclosure relates to a method for accessing an array of memory cells, comprising the steps of storing user data in a plurality of memory cells of a memory array, storing, in a counter associated to the array of memory cells, count data corresponding to a number of bits in the user data having a predetermined first logic value, applying a read voltage to the memory cells to read the user data stored in the array of memory cells, applying the read voltage to the cells of the counter to read the count data stored in the counter and to provide a target value corresponding to the number of bits in the user data having the first logic value, wherein, during the application of the read voltage, the count data are read simultaneously to the user data in such a way that the target value is provided during the reading of the user data, and based on the target value of the counter, stopping the application of the read voltage when the number of bits in the user data having the first logic value corresponds to the target value. A related memory device and a related system are also disclosed.

公开(公告)号：US11869587B2

公开(公告)日：2024-01-09

申请号：US17495423

申请日：2021-10-06

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Riccardo Muzzetto ,  Umberto Di Vincenzo

IPC: G11C13/00 ,  G11C16/04 ,  G11C7/10 ,  G11C16/28 ,  G11C11/22 ,  G11C7/14

CPC classification number: G11C13/004 ,  G11C7/1051 ,  G11C11/2255 ,  G11C11/2273 ,  G11C16/0483 ,  G11C16/28 ,  G11C7/14 ,  G11C2013/0054

Abstract: Methods, systems, devices, and techniques for read operations are described. In some examples, a memory device may include a first transistor (e.g., memory node transistor) configured to receive a precharge voltage at a first gate and output first voltage based on a threshold of the first transistor to a reference node via a first switch. The device may include a second transistor (e.g., a reference node transistor) configured to receive a precharge voltage and output a second voltage based on a threshold of the second transistor to a memory node via a second switch. The first voltage may be modified by a reference voltage and input to the second transistor. The second voltage may be modified by a voltage stored on a memory cell and input to the first transistor. The first and second transistor may output third and fourth voltages to be sampled to a latch.

公开(公告)号：US11715508B2

公开(公告)日：2023-08-01

申请号：US17387301

申请日：2021-07-28

Applicant: Micron Technology, Inc.

Inventor： Hyun Yoo Lee ,  Suryanarayana B. Tatapudi ,  Huy T. Vo ,  Ferdinando Bedeschi ,  Umberto Di Vincenzo ,  Riccardo Muzzetto

IPC: G11C11/22 ,  G11C11/4094 ,  G11C11/4091

CPC classification number: G11C11/2273 ,  G11C11/221 ,  G11C11/4091 ,  G11C11/4094

Abstract: Methods, systems, and devices for a source follower-based sensing architecture and sensing scheme are described. In one example, a memory device may include a sense circuit that includes two source followers that are coupled to each other and to a sense amplifier. A method of operating the memory device may include transferring a digit line voltage to one of the source followers and transferring a reference voltage to the other source follower. After transferring the digit line voltage and the reference voltage, the source followers may be enabled so that signals representative of the digit line voltage and the reference voltage are transferred from the outputs of the source followers to the sense amplifier for sensing.